JPH0286031U - - Google Patents
Info
- Publication number
- JPH0286031U JPH0286031U JP10780888U JP10780888U JPH0286031U JP H0286031 U JPH0286031 U JP H0286031U JP 10780888 U JP10780888 U JP 10780888U JP 10780888 U JP10780888 U JP 10780888U JP H0286031 U JPH0286031 U JP H0286031U
- Authority
- JP
- Japan
- Prior art keywords
- channel
- relay
- switching
- gate
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Relay Circuits (AREA)
Description
第１図は本考案に係るリレー切替え回路の一実
施例の接続図、第２図は第１図回路によつて切替
えられるリレー接点の構成説明図、第３図は第１
図回路の動作を説明するための図である。
１〜６…チヤネル切替え回路、Ｃ，Ｅ…アンド
・ゲート、Ｄ，Ｆ，Ｇ…インバータ、ＲＬ…リレ
ー、ａ，ｂ…リレーコイル、Ａ，Ｂ…チヤネル切
替え用パルス、ＤＬ…遅延回路。
Fig. 1 is a connection diagram of one embodiment of the relay switching circuit according to the present invention, Fig. 2 is an explanatory diagram of the configuration of the relay contacts switched by the circuit of Fig. 1, and Fig.
FIG. 3 is a diagram for explaining the operation of the circuit shown in FIG. 1-6... Channel switching circuit, C, E... AND gate, D, F, G... Inverter, RL... Relay, a, b... Relay coil, A, B... Channel switching pulse, DL... Delay circuit.
Claims (1)
を切替えるリレー切替え回路において、各チヤネ
ルを夫々そのチヤネルのリレーコイルに出力端子
が接続される一対のアンド・ゲートを備え、一方
のアンド・ゲートにチヤネル選択信号と一定の時
間間隔を於いて発生するチヤネル切替え用のパル
スが印加され、他方のアンド・ゲートにインバー
タを介して得られる前記一方のアンド・ゲートの
出力と遅延回路を介して得られる前記チヤネル切
替え用のパルスを印加するように構成してなるリ
レー切替え回路。 In a relay switching circuit that switches a plurality of channels by switching a relay, each channel is provided with a pair of AND gates whose output terminals are connected to the relay coil of that channel, and one AND gate is connected to a channel selection signal. Pulses for channel switching that occur at regular time intervals are applied, and the output of the one AND gate obtained through the inverter and the channel switching pulse obtained through the delay circuit are applied to the other AND gate. A relay switching circuit configured to apply a pulse of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10780888U JPH0286031U (en) | 1988-08-16 | 1988-08-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10780888U JPH0286031U (en) | 1988-08-16 | 1988-08-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0286031U true JPH0286031U (en) | 1990-07-06 |
Family
ID=31342552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10780888U Pending JPH0286031U (en) | 1988-08-16 | 1988-08-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0286031U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5086240A (en) * | 1973-11-29 | 1975-07-11 |
-
1988
- 1988-08-16 JP JP10780888U patent/JPH0286031U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5086240A (en) * | 1973-11-29 | 1975-07-11 |