JPH0287237A - Execute instruction control system - Google Patents

Abstract

PURPOSE:To reduce the processing burden of a routine for monitor by using the signal of an instruction extracting event, which is held when a target instruction is executed, and executing program interruption control. CONSTITUTION:An instruction extracting event detecting signal B-IFPER of the target instruction detected in a B cycle of the flow of an EXECUTE instruction is held by a latch 12 in a W cycle and goes to be a W-EX-PER. In an E cycle of the target instruction, the output signal W-EX-PER of the latch 12 is fetched and a W-EX-TARGET-IFPER is set to a latch 13. Accordingly, even if the instruction extracting event concerning the target instruction is detected in the B cycle of the EXECUTE instruction, the W-EX-TARGET-IFPER is not generated if the target instruction is not executed. Then, PER-PENDING can not be set. Thus, program interruption is not executed by a detected result for the instruction extracting event of the target instruction and the processing burden is reduced.

Description

[Detailed Description of the Invention] [Summary] E during trace recording of a program in an information processing device
Regarding the XECUTE command control method.

When an execution exception due to the execution of a double EXECUTE instruction overlaps with the detection of an instruction fetch event of the target instruction of the second EXECLITE instruction, the processing of the monitor routine is performed by preventing unnecessary recording of the latter event. at
The purpose is to reduce O.

means for detecting an instruction fetch event of the target instruction during processing of the EXECUTE instruction; means for holding the signal of the detected instruction fetch event until the execution of the target instruction; and means for detecting execution of the target instruction; and is configured to perform program interrupt control using the held instruction fetch event signal when executing the target instruction.

(Industrial Application Field) The present invention relates to an EXECUTE command control method when recording a trace of a program in an information processing device.

The EXECUTE instruction is an instruction to execute an instruction at an address specified in the instruction (referred to as a target instruction), and after the execution of the target instruction is completed, the command returns to the instruction next to the original EXECUTE instruction.

In the present invention, if the target instruction of this EXECUTE instruction becomes the EXECUTE instruction again due to a program creation error, even if the target instruction of the second EXECUTE instruction causes a program interrupt that records the event, the event record will not be recorded. To provide an improved control technique to prevent this from occurring.

[Conventional technology]

Many information processing devices are equipped with an event recording function (PER Niprogram Event Recording) for tracing instructions executed in a program for the purpose of diagnosing the program when it malfunctions or evaluating its performance.

This event recording function can record nine different types of events, including instruction fetch event recording (IFPER).
In this case, specify a certain program area in memory in advance when setting the function.

Detects an instruction fetch event to determine whether an instruction within a specified area is fetched, generates a program interrupt and starts an event recording routine when an instruction within the specified area is fetched, and interrupts to indicate instruction fetch event detection Record the code.

On the other hand, in the conventional EXECUTE command control method.

If the event recording function is set, an instruction fetch event for the target instruction is detected when an EXECUTE instruction is executed, and a bending latch for causing a program interrupt is immediately set.

By the way, there are cases where the target instruction of the EXECUTE instruction in the program becomes the SNAP XE CUTE instruction again. Since this is usually caused by a program creation error, a program interrupt is generated as an execution exception to interrupt the nine programs.

FIG. 4 illustrates an example of a program including such double EXECUTE instructions, where l is memory. 2
and 3 are the control registers CRIO and CRI, respectively.
I, and addresses A and B defining the upper and lower ends of the program area for recording events on memory I are set.

Here, the instructions at addresses n and m are EXECUTE instructions, and in each, 4 indicates the OP code section and 5 indicates the address section of the target instruction. In this case, the EXECUTE instruction at address n
The target instruction of the ECUTE instruction is EXE at address m.
It is a CUTE command.

Also, the target instruction of the EXECUTE instruction at address m is
+ is another command at the address.

FIG. 5 shows a control flow of an EXECUTE command in a conventional pipeline type information processing device.

■ in the diagram is the flow of the first EXECUTE instruction ■ is the flow of the second EXECUTE instruction (2ND EXECUTE)
This is the flow. Also, the glue in each flow, A, T, B,
, W are sequential cycles (or processing stages) of the pipeline, D is instruction decode, A is operand address operation, T is address translation 9, B is buffer access, E is operation execution, and W is result Each cycle of writing is represented.

The EXECUTB instruction itself is processed in one flow as in (1) and (2). The target of the EXECUTE command is also E.
If it is an XECUTE instruction, an execution exception is indicated and causes a program interrupt.

In other words, when this execution exception is detected, the 2ND of ■
EXECUTE (7) W cyclete, W XV (
W cycle! ! XCEPTION VALIO) is raised, instruction processing is interrupted, and 1 interrupt processing is started.

On the other hand, in the B cycle of 2ND EXECUTE in ■, the instruction fetch event B IFPER is detected, and in the W cycle, PERPENDIN, which generates a program interrupt, is detected.
G is set.

If the EXECUTE instruction is executed twice in this way, an execution exception will be detected in the execution of the second EXECUTE instruction, and a program interrupt will be generated with an interrupt code representing the double execution of the EXECUTE instruction (for example, ° “03”). ) is set and the second EXECUTE
When an instruction fetch event of the target instruction (instruction at address m+ in Figure 4) is detected at the time of execution of the instruction, a program interrupt is generated and an interrupt code representing the event record (for example, ° "8x" is Note that the value of "X" may be any value).

As a result, the interrupt codes of the two program interrupts will be reported together (the interrupt code in the above example is 83°).However, in reality, the target instruction of the second EXECUTE instruction 1 interrupt code “8” because the program is interrupted before it is executed.
8X° in 3″.

This part was redundant.

When RAM interrupts overlap, their respective interrupt codes are reported together and logged by the event recording routine.

Therefore, the instruction fetch event of the target instruction that is not originally executed in the second EXECUTE instruction must be deleted from the event record, and the event record monitoring routine searches for and deletes this extra event record. It was being processed.

According to the present invention, when an execution exception due to the execution of a double EXECUTE instruction and an instruction fetch event detection of the target instruction of the second EXECUTE instruction overlap, the latter event is prevented from being recorded redundantly, and the monitoring is performed. The purpose is to reduce the processing load of routines.

[Problem to be solved by the invention]

In the conventional EXECtJT command control method, the
Program interrupt due to execution of XECUTE instruction, 2
Programming by detecting an instruction fetching event of a target instruction in the th EXECUTE instruction (means for solving the problem) The present invention prevents a program interrupt by detecting an instruction fetching event of a target instruction on the condition that the target instruction of the EXECUTE instruction has been executed. to occur,
When a program interrupt occurs due to an execution exception when an EXECUTE instruction is executed twice, the program interrupt is not caused by detection of an instruction fetch event of the target instruction of the 32nd EXECUTE instruction.

Therefore, the present invention provides means for detecting an instruction fetch event of a target instruction during processing of an EXECUTE instruction, means for holding a signal representing the detected instruction fetch event until execution of the target instruction, and means for detecting an instruction fetch event of a target instruction. means for detecting that the target instruction is being executed, and generating a signal for activating a program interrupt with a signal indicative of a held instruction fetch event only when the target instruction is executed.

FIG. 1 shows the basic structure of the present invention in an exemplary manner.

FIG. 1 shows a part of a pipeline control circuit to which the present invention is applied, and 11 to 14 are latches.

15 is an AND circuit, and 16 is an OR circuit.

Latch 11 Manual B [FPER EXECUTE
This is an instruction fetch event detection signal that is output in the B cycle of the flow for executing an instruction, and is set and held in the latch 11 by the timing signal B RELEASE that gates the clock at the end of the B cycle.

W EX-PER of latch 12 output is EXECLJ
At the end of the E cycle of the flow of the TE instruction, the timing signal E-RELEASE causes the latch 11 output B to
This is the output obtained by taking IFRER into the latch 12 and holding it there.

Latch 13 output (7) W EX-TARGET-IF
PER outputs the timing signal E REL at the end of the E cycle of the flow of the EXECUTE instruction.
This is the output obtained by capturing and holding the WEX PER of the latch 12 output with EASE.

One input W EXECTAG of the AND circuit 15 is
It is output at cycle W of the flow of the target instruction and indicates that the executed instruction is the target of the EXECUTE instruction.

W EX-TARGET IFPER and WEXEC
The two TAG signals are matched by an AND circuit 15, and the resulting signal is held in the latch 14 and is also ORed.
It is applied to one input of the circuit 16.

The OR circuit 16 takes the logical sum of the outputs of the AND circuit 15 and the latch 14, and requests event recording.
Outputs NDING to cause a program interrupt.

[Effect]

The operation of the basic configuration of the present invention shown in FIG. 1 will be explained using the flowchart shown in FIG. 2.

Instruction fetch event detection signal B I of the target instruction detected in the B cycle of the flow of the EXECUTE instruction in ■
FPER is held in the latch 12 for W cycles as shown in (2), and becomes W EX PER.

The D cycle of the target instruction in ■ is EXECUT in ■.
It is started at the timing of W cycle of the flow of E instruction.
In the next A cycle, the signal W EXECTAG indicating that it is the target of the EXECUTE command as shown in ■
is output and applied to one input of the AND circuit 15.

In the E cycle of the target instruction (2), the output signal W EX PER of the latch 12 is taken in and W-EX TARGET-IFPER is set in the latch 13. In the next W cycle, AND circuit 154;! WEX
TARGET I FPER and W-EXECTA
(7) PER-PENDING is sent and a program interrupt is performed.

As a result, even if an instruction fetch event for the target instruction is detected in the B cycle of the EXECUTE instruction, if the target instruction is not executed, W E)lTA
RGET-I FPERf) < not generated, PERPE
Since NDING cannot be set, programming is not performed based on the detection result of the instruction fetch event of the target instruction.

〔Example〕

FIG. 3 shows the flow of EXECUTE command control according to one embodiment of the present invention. The flow shown in FIG. 3 is a case where the target instruction of the EXECUTE instruction is the target instruction again in the flow shown in FIG. 2.

■ in Figure 3 is the first EX-ECUTE command, and ■ is the E of ■.
The target EXECtJTE instruction of the XECUTE instruction, ■ is the flow of the detection signal of the double EXECUTE instruction, ■
is the flow of the instruction fetch event detection signal BIFPER for the target instruction of the XECUTE instruction.

Fetch cycles I, IT, I of the target instruction from the T cycle to the E cycle of the EX CUTE instruction in ■
B is executed, and the EXECUTE instruction (3) is taken out as a target instruction and executed.

Double EXE of ■ in A cycle of EXECUTE command of ■
The CUT instruction is detected and the detection signal EX is set (an existing detection circuit is used).
-GO is set and a program interrupt is performed.

On the other hand, the instruction fetch event of the target instruction is detected in the B cycle of the EXECUTE instruction (2).

Detection signal B IFPER (2) is generated. but,
Due to an execution exception due to double EXECUTE instruction detection in the W cycle of ■, PROC[! 5S-5WITCH-
G.

When W EX TARGET IFPE is set, do not set the latch 13 in FIG.
By preventing R from being generated, PERP
Generation of ENDING is blocked.

No instruction fetch event reporting is performed for the target instruction of the second EXECUTE instruction.

On the other hand, in FIG. 3, if the EXECUTE command (■) is the first EXECUTE command, the PROCES (■)
Since S-3 TCH-Go is not generated and execution exception interrupts are not performed, PERPENDING is generated for the target instruction as explained in FIG.

16: OR circuit [Effect of the invention] According to the present invention, when the EXECUTE instruction is executed twice, the
Since reporting of instruction fetch event detection is blocked for the target instruction of the th EXECUTE instruction, redundant event records are not recorded and deletion processing by the event record monitoring routine is no longer necessary, significantly reducing the processing load in 5. can do.

Claims (1)

[Scope of Claims] Means for detecting an instruction fetch event of a target instruction during processing of an EXECUTE instruction; means for retaining a signal of the detected instruction fetch event until execution of the target instruction; an EXECUTE instruction control method, comprising means for detecting execution, and performing program interrupt control using the held instruction fetch event signal when the target instruction is executed.