JPH0287568A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semiconductor technology, and more particularly to technology that is effective when applied to the manufacture of complementary MISFETs.

[Prior Art] In complementary MISFETs, in order to ensure latch-up resistance, the distance from the semiconductor region (diffusion layer) of the source/train of one MISFET to the boundary of the well where the other MISFET is configured must be set sufficiently. However, if a structure with such a sufficient distance is created, high integration of semiconductor integrated circuits will be hindered. Therefore, in order to eliminate such inconvenience, recently,
Complementary MI with a structure in which the source/drain semiconductor regions around the well or inside the well are surrounded by a power supply region that is a semiconductor region of the same conductivity type as the well but with a higher concentration than the well.
SFET is being considered.

A semiconductor device having such a structure is described in, for example, Japanese Patent Laid-Open No. 71260/1983.

By the way, in order to realize such a complementary MISFET, it is necessary to surround the source/drain semiconductor regions around the well or inside the well with a continuous high concentration semiconductor region (power supply section).

This is because if there is a cut in the power feeding section, the latch-up strength will decrease in that region.

Therefore, for example, in a conventional inverter, etc., as shown in FIG. It was composed of connecting wiring 3a. The reason is as follows.

That is, conventionally, the gate electrode 1 of MISFET,
2, the source/drain semiconductor regions 4 and 7 were formed by ion implantation using self-aligned lines. Furthermore, when forming the source/drain semiconductor region 7 of the MISFET on the side where the well 5 does not exist, ions are simultaneously implanted into the region where the power supply part is to be formed, thereby forming a high concentration semiconductor region (power supply part) in the armpit region. )6 was formed. In that case, the gate electrodes 1 and 2 in the complementary MISFET and the gate wiring 3 connecting them.

If it has already been formed before forming the high concentration semiconductor region 6 that will become the power supply section, a part of the gate wiring 3 will already be above the region where the power supply section is to be formed when the high concentration semiconductor region 6 is formed. Since the gate line 3 crosses the gate line 3, the gate line 3 functions as a mask during ion implantation, and a cut-off power supply portion, that is, a high concentration semiconductor region 6 is created. Therefore, in order to eliminate such inconveniences, in manufacturing a conventional complementary MISFET, the upper part of the power supply part of the gate wiring 3 is connected by a connecting arrangement i3a after the formation of the high concentration semiconductor region 6.

In FIG. 3, reference numeral 8 represents a Vcc wiring, and reference numeral 9 represents a Vss wiring.

[Problems to be Solved by the Invention] However, a complementary MISFE having a structure in which the upper part of the power feeding part in the gate wiring 3 is connected by the wiring 3a,
There were the following problems with T. That is, when providing the connecting wiring 3a, connecting parts (contact parts) must be provided in the inner part of the well 5 and the outer part of the well 5. Therefore, the layout area becomes large, which hinders the miniaturization and high integration of semiconductor integrated circuits.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the reliability of a semiconductor integrated circuit and achieve miniaturization and high integration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in Suido are summarized as follows.

That is, in the manufacturing method of a semiconductor device according to the present invention, in manufacturing a semiconductor device in which an N-channel MISFET and a P-channel MISFET are mounted, a high concentration semiconductor region is formed before forming a gate electrode of the MISFET and a gate wiring connected thereto. is formed, and then the gate electrode and gate wiring are simultaneously formed.

[Operation] According to the above-mentioned means, the high concentration semiconductor region which becomes the power supply part is formed before the formation of the gate wiring.
It is possible to form a continuous high-concentration semiconductor region under the gate wiring, which increases the latch-up strength.Furthermore, there is no need to provide connecting wiring in the middle of the gate wiring, which reduces the layout area. The above objectives of improving reliability, miniaturization, and high integration of integrated circuits are achieved.

[Example] Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained based on the drawings.

FIG. 1 shows a planar layout of a semiconductor device obtained by applying the example.

In the semiconductor device of this embodiment, a P-type silicon substrate 11 as shown in FIG. 2 is used as a substrate, and N wells 12 are formed on this silicon substrate 11.
Further, an N+ type semiconductor region (power supply section) 13 is formed in this well 12, and this N1 type semiconductor region 13 is connected to the vccii! 1IX25. Also, on this N well 12 side, a P channel M
An ISFET is formed, while an N4-Yanel MIS is formed in a region of the silicon substrate 11 where the well 12 is not formed.
FET is configured. And the above P channel MI
The SFET and the N-channel MISFET are separated by a field oxide film 14 and a P+ channel stopper region 24 below it. Here, P channel MISFE
T is composed of a P-type semiconductor region (source/drain) 15 formed in the well 12 and a gate electrode (portion that actually functions as a gate) 17 provided on the well 12 via a gate insulating film. ing. The N-channel MISFET also includes an N-type semiconductor region (source/drain) 18 formed in a silicon substrate 11 and a gate electrode 2 provided on the silicon substrate 11 with a gate insulating film interposed therebetween.
It is composed of 0.

Then, the gate electrode 17 of the P-channel MISFET and the N
The gate electrode 20 of the channel MISFET is mutually connected by a gate wiring 21 made of a gate electrode material.

Note that one of the semiconductor regions 15 of the P-channel MISFET and one of the semiconductor regions 18 of the N-channel MISFET are connected by a wiring 22.

The other semiconductor region 15 of the P-channel MISFET is connected to the Vcc wiring 25, and the other semiconductor region 18 of the N-channel MISFET is connected to the Vss wiring 11A23.

Next, the manufacturing method of this example will be explained using FIGS. 1 and 2.

First, an N-well 12 is formed in a P-type silicon substrate 11, thereby separating the P-channel MISFET region and the N-channel MISFET region.

Next, element isolation is performed. This element isolation is achieved by field oxide film 14 and P+ channel stopper region 24 formed under it. Thereafter, using a photoresist film having an opening corresponding to the power supply part as a mask, an N type impurity is introduced into the region where the power supply part is to be formed by, for example, ion implantation to form an N+ type semiconductor region (power supply part) 13.

Next, after forming a gate insulating film, gate electrodes 17 and 20 are formed on the gate insulating film, and at the same time, a gate wiring 21 is formed. Then, if necessary, L D D
(Lightly doped draft) Light ion implantation and sidewalls (spacers) are performed to form a structure, and then semiconductor regions 15 and 18 of an N-channel MISFET and a P-channel MISFET are formed using a mask twice.

Then, after forming an MA film 26 such as PE3G, a contact hole is opened, a wiring 26 is formed, and a P-channel MISF
One of the semiconductor regions 15 of the ET and the N-channel MISFET
and one of the semiconductor regions 18. Thereafter, various steps are performed to complete the semiconductor device shown in FIGS. 1 and 2.

According to the above semiconductor device, the following effects can be obtained.

According to the method described above, since the N+ semiconductor region 13 serving as the power supply section is formed before forming the gate interconnect 11A21, an unbroken N1 type semiconductor region 13 is formed below the gate interconnect 21, resulting in a latch. In addition, there is no need to provide a connecting wire in the middle of the gate wiring 21 as in the past, and as a result, the layout area can be reduced, which leads to improved reliability, miniaturization, and high integration of semiconductor integrated circuits. It will be possible to achieve this goal.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

In the embodiment described above, an N-well 12 is formed in a P-type silicon substrate 11, and a P-channel MI
We have explained what constitutes SFET, but conversely, N
The present invention can also be applied to a method in which a P-well is formed in a type silicon substrate and an N-channel MISFET is configured within this P-well, and furthermore, it can be applied to a method for manufacturing a double-well type semiconductor device.

Furthermore, in the above-described embodiments, the case where the power supply section is provided inside the well 12 has been described, but the method for manufacturing a semiconductor device in which the power supply section is provided outside the well 12 and connected to the well 12 may also be described. can also be applied.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, according to the method of manufacturing a semiconductor device according to the present invention, M
The power supply section is formed before forming the gate wiring that connects the gates of the ISFETs, and then the gate electrode and the interconnections are formed at the same time, so it is possible to form a seamless power supply section. Moreover, there is no need to provide a connecting wire in the middle of the gate wiring, and as a result, the reliability of the semiconductor integrated circuit can be improved, and miniaturization and high integration can be achieved.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the planar layout of a semiconductor device obtained by applying an embodiment of the semiconductor device manufacturing method according to the present invention, and FIG. 2 is a plan view taken along the line II-II of the semiconductor device in FIG. Longitudinal cross-sectional view. FIG. 3 is a plan view showing the planar layout of a conventional semiconductor device. 12...well, 13...N+ semiconductor region (high concentration semiconductor region), 17.20...gate electrode, 2
1...Gate wiring. Figure 1 Rod Figure 2 - Mutual

Claims (1)

[Claims] 1. N-channel MISFET and P-channel MISFET
When forming a power feeding section consisting of a highly doped semiconductor region of the same conductivity type as the well around or inside the well for separating the MISFET, the high concentration 1. A method of manufacturing a semiconductor device, characterized in that a doped semiconductor region is formed, and then the gate electrode and gate wiring are formed simultaneously. 2. Claim 1, wherein the gate electrode and the gate wiring are formed of polycrystalline silicon.
A method of manufacturing the semiconductor device described above.