JPH028785A - electronic memo pad - Google Patents

electronic memo pad

Info

Publication number
JPH028785A
JPH028785A JP1037563A JP3756389A JPH028785A JP H028785 A JPH028785 A JP H028785A JP 1037563 A JP1037563 A JP 1037563A JP 3756389 A JP3756389 A JP 3756389A JP H028785 A JPH028785 A JP H028785A
Authority
JP
Japan
Prior art keywords
time
circuit
carry
coincidence
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1037563A
Other languages
Japanese (ja)
Inventor
Toshio Orii
折井 俊雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1037563A priority Critical patent/JPH028785A/en
Publication of JPH028785A publication Critical patent/JPH028785A/en
Pending legal-status Critical Current

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Landscapes

  • Electric Clocks (AREA)
  • Calculators And Similar Devices (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

PURPOSE:To avoid wasteful power consumption by performing no coincidence comparison of time data until the next unit time arrives when there is no schedule in a unit time within a data memory. CONSTITUTION:A signal inputted to a unit time circuit 10 from a clock circuit 19 is a carry signal of a unit time (e.g., a carry-up signal of 10 min or one hr). Therefore, when the carry-up signal of one-hour position is inputted from a circuit to the circuit 10, the circuit 10 outputs the time (set to a-o'clock) at that time at first to input the same to the second collation circuit 11. The time in the data memory 5 inputted to the circuit by one address by a control circuit 6 and each time is compared with a-o'clock. At the time of coincidence, time data is transmitted to a coincidence circuit 4 at every min carry-up to perform comparison or necessary display. At the time of non-coincidence, the next hr carry-up is performed after waiting. By this method, when there is no schedule for a time of 00-59 min in the memory 5, it is unnecessary to perform coincidence comparison and, therefore, wasteful power consumption is avoided.

Description

【発明の詳細な説明】 本発明は電子的に日時及び文章を記憶し、既当時刻到来
時に、何らかの手段で表示する電子メモ帳の時刻照合法
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time verification method for an electronic memo pad that stores date, time and text electronically and displays the date and time by some means when the current time arrives.

電子メモ帳の機能を説明するための従来の例を第1図に
示す。同図中1は入力及び制御用キー(複数)である。
A conventional example for explaining the functions of an electronic memo pad is shown in FIG. In the figure, reference numeral 1 indicates input and control keys (a plurality of keys).

2は記憶された内容の表示部である。第1表に記憶され
る文章の一形態を示す。
2 is a display section for displaying stored contents. Table 1 shows one type of text to be stored.

1980年1月24日 A?110時30分C0NFE
NCE1980年1月24日 AM11時45分旺ET
ING1980年1月24日 PM 3時O分子ELH
PIIONE第1表 操作者は年、月、日、時、分、文章をキーにより入力し
て、データメモリ内への格納を命令するキー(第1図中
では番キー)を押して記憶操作を完了する。
January 24, 1980 A? 110:30 C0NFE
NCE January 24, 1980 11:45 AM ET
ING January 24, 1980 PM 3 o'clock O molecule ELH
PIIONE Table 1 The operator inputs the year, month, day, hour, minute, and text using the keys, and then presses the key (the number key in Figure 1) that commands storage in the data memory to complete the memorization operation. do.

一方記憶回路としては、第2図記憶回路に示す如くの構
造をなし、キーボードlからの信号をキーボード用バッ
ファメモリの内容をデータメモリ3の空番地に格納する
。第2図の例では、斜線部にすでに有効データが格納さ
れているものとし、空欄は記憶されるべきデータの番地
を表しているので、前述のデータは5番地に格納される
ことになる。
On the other hand, the storage circuit has a structure as shown in FIG. In the example of FIG. 2, it is assumed that valid data has already been stored in the shaded area, and the blank space represents the address of the data to be stored, so the aforementioned data will be stored at address 5.

一方9は計時機能を有する回路(時計回路)であり、年
、月、日、時、分のデータを発生する。
On the other hand, 9 is a circuit (clock circuit) having a timekeeping function, which generates year, month, day, hour, and minute data.

そのデータは4−数回路の入力となる。計時回路9にお
ける1分桁の桁上信号を出力として6に示すデータメモ
リ制御部に入力して、データメモリ内の各番地の年〜分
データを4−数回路に転送して、一致照合をとる。一致
であれば、その番地のデニタを7表示用メモリに転送し
、8に示す表示回路で表示する。もし不一致であれば6
はデータメモリの番地を1番地分だけインクリメントし
て再度−数回路にて一致照合をおこなうことになる。こ
のように分桁での桁上信号を6の制御回路入力として1
分毎に一致回路4で照合をおこなう時、データメモリ内
にデータの記憶されていない時刻にも照合操作をおこな
うわけであるから、そのために、無駄な電力を使用する
ことになる。
The data becomes an input to a 4-number circuit. The 1-minute digit carry signal from the clock circuit 9 is input as an output to the data memory control section 6, and the year to minute data at each address in the data memory is transferred to the 4-number circuit for matching. Take. If there is a match, the data at that address is transferred to the display memory 7 and displayed on the display circuit 8. If there is a mismatch, 6
In this case, the address of the data memory is incremented by one address, and the match verification is performed again using the minus number circuit. In this way, the carry signal at the minute digit is input to the control circuit of 6, and 1
When the match circuit 4 performs verification every minute, the verification operation is also performed at times when no data is stored in the data memory, which results in wasted power.

特に電子メモ帳のように、携帯機器では電源は、電流零
量の少ない電池であり、無駄な消費は避けるのが望まし
い。かと言って、時刻の照合を10分桁の桁上時におこ
なえば、5分単位の記憶は不可能となってしまうという
ディレンマが生ずる。
Particularly in portable devices such as electronic memo pads, the power source is a battery with a low current draw, and it is desirable to avoid unnecessary consumption. However, if the time is checked when the 10-minute digit is reached, a dilemma arises in that it becomes impossible to memorize the data in units of 5 minutes.

本発明は前述の欠点を改良したものである。第3図に回
路図を示す。第2図と同一機能の回路は同一番号で示す
。同図19は、時計回路であり、19−10に入力され
る信号は単位時間(例えば10分の桁上信号又は1時間
のそれ)の桁上信号である。いま、19の1時間桁の桁
上信号がlOに示す単位時開時回路に入力されると、1
0からは始めにその時の時間(a時とする)が出力され
て、11に示す第2照合回路に入力される。11には、
6により、データメモリ中の時刻が一番地ずつ入力され
、それぞれの時刻とa時が比較されて、一致のときは、
分桁上毎に19→4に時刻データを転送し、比較及び必
要な表示をおこなう。
The present invention ameliorates the above-mentioned drawbacks. Figure 3 shows the circuit diagram. Circuits with the same functions as those in FIG. 2 are indicated by the same numbers. 19 is a clock circuit, and the signal inputted to 19-10 is a carry signal of a unit time (for example, a carry signal of 10 minutes or that of 1 hour). Now, when the 1 hour digit carry signal of 19 is input to the unit hour open time circuit shown at lO, 1
Starting from 0, the current time (assumed to be time a) is outputted and inputted to the second verification circuit shown at 11. In 11,
6, the times in the data memory are input one by one, each time is compared with time a, and if they match,
Time data is transferred from 19 to 4 every minute digit, and comparison and necessary display are performed.

もし一致のない時(データメモリ中に既当時刻がない時
)は次の時桁上まで待機する。このようにすることによ
り、データメモリ中に00分〜59分間に予定が無い場
合は、−数比較をおこなわなくてすむため、前述のよう
に、予定が記憶されていない時に、−数比較をおこなっ
て無駄な電力を浪費することが減る。更に、分単位での
記憶は可能であり、前述のようなディレンマが解消でき
る。
If there is no match (when there is no existing time in the data memory), wait until the next time digit. By doing this, if there is no schedule from 00 minutes to 59 minutes in the data memory, there is no need to perform a -number comparison. This reduces unnecessary power wastage. Furthermore, it is possible to store data in minutes, which eliminates the dilemma described above.

よって本発明は、携帯用電子メモに最適な時刻照合法で
ある。
Therefore, the present invention is a time verification method most suitable for portable electronic memos.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、電子メモ帳を示す図。 第2図は、従来の記憶回路を示す図。 第3図は、本発明の回路例を示す図。 第11囚 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜三部他1名 第2図 FIG. 1 is a diagram showing an electronic memo pad. FIG. 2 is a diagram showing a conventional memory circuit. FIG. 3 is a diagram showing an example of the circuit of the present invention. Prisoner 11 that's all Applicant: Seiko Epson Corporation Agent: Patent attorney Kizobe Suzuki and 1 other person Figure 2

Claims (1)

【特許請求の範囲】[Claims] データメモリに日時又は予定などを記憶しておき、計時
回路による時刻と、記憶された時刻とが一致した時、表
示体を駆動して、時刻到来を告げる電子メモ帳において
、単位時間内のデータメモリ中の予定の有無を検出し、
有時においては、単位時間内の微小時間にわたり詳細な
照合をおこない、無時には、次の単位時間の到来まで、
照合動作を停止することを特徴とする電子式メモ帳。
The date and time or schedule are stored in the data memory, and when the time measured by the clock circuit and the stored time match, the display is driven and the electronic memo pad announces the arrival of the time. Detects the presence or absence of a schedule in memory,
When there is a time, detailed verification is carried out over a minute time within a unit time, and when there is no time, until the arrival of the next unit time,
An electronic memo pad characterized by stopping the verification operation.
JP1037563A 1989-02-17 1989-02-17 electronic memo pad Pending JPH028785A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1037563A JPH028785A (en) 1989-02-17 1989-02-17 electronic memo pad

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1037563A JPH028785A (en) 1989-02-17 1989-02-17 electronic memo pad

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP55174163A Division JPS5797488A (en) 1980-12-09 1980-12-10 Electronic memo note

Publications (1)

Publication Number Publication Date
JPH028785A true JPH028785A (en) 1990-01-12

Family

ID=12500991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1037563A Pending JPH028785A (en) 1989-02-17 1989-02-17 electronic memo pad

Country Status (1)

Country Link
JP (1) JPH028785A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002089558A (en) * 2000-08-03 2002-03-27 Ina Waelzlager Schaeffler Ohg Cover belt device for linear guide

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002089558A (en) * 2000-08-03 2002-03-27 Ina Waelzlager Schaeffler Ohg Cover belt device for linear guide

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