JPH028941A - Microprocessor - Google Patents

Abstract

PURPOSE:To check the internal state of a microprocessor while the microprocessor is operated and at the same time, to eliminate the necessity of an exclusively used chip, etc., by providing an input-output terminal for outputting internal state data, instruction recognition circuit, output circuit, etc. CONSTITUTION:An instruction recognition circuit 11 recognizes and discriminates control instructions inputted from an external circuit 5 at prescribed timing through a communication line 4 and input-output terminal 3a. A readout circuit 13 reads out the internal state data from a prescribed or all registers 7 in accordance with the control signal outputted from the circuit 11. An output circuit 12 sends the internal state data read out by the circuit 13 to the circuit 5 through the terminal 3a and line 4. Namely, the terminal 3a is used in a split control when input and output cycles are alternately arranged, and when an inputted control instruction requests the report of the program status, all of the internal state data are outputted in the next output cycle. Therefore, the internal state of a microprocessor 1 can be checked and reported while the microprocessor 1 is operated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprocessor whose internal state can be examined during arithmetic operations.

(Prior Art) When developing a microprocessor or a program for a microprocessor, it is necessary to know the internal state, ie, the values of various registers, program status, etc., during its operation.

Conventionally, the following methods have been used for this purpose.

That is, the control program on the ROM or RAM in the system is operated at a predetermined timing using functions such as breakpoints supported by the microprocessor. This control program reads the internal state of the microprocessor at that point in time. Therefore, in this case, the original operation of the microprocessor is stopped, the control program occupies the microprocessor, and the microprocessor notifies the outside of the internal state.

Another method is to use, for example, a so-called in-circuit emulator that operates in the same manner as a microprocessor. If the in-circuit emulator is controlled by a predetermined control program to notify the internal state, it becomes possible to notify the internal state in more detail. For example, all instructions executed on a microprocessor can be reported in almost real time.

Furthermore, when a specified instruction such as the I10 instruction is executed, the microprocessor stops and notifies external circuits to that effect.

(Problems to be Solved by the Invention) However, the conventional method as described above has the following problems.

First, in the method using functions such as breakpoints, the operation of the microprocessor must be stopped when notifying the internal state. Therefore, there is a problem in that it lacks so-called real-time performance.

On the other hand, the method using an in-circuit emulator requires special hardware to emulate the operation of a microprocessor, and requires complicated steps such as mounting a dedicated chip on a board. In addition, there remains the problem of mounting space.

The present invention has been made with attention to the above points, and an object of the present invention is to provide a microprocessor that can check the internal state of the microprocessor while it is operating, and that does not require a dedicated chip or the like. It is something.

(Means for Solving the Problems) The microprocessor of the present invention is provided separately from input/output terminals for normal arithmetic processing data, and inputs control commands from an external circuit during the normal arithmetic processing operations. an input/output terminal for outputting internal state data in response to a control command; a command recognition circuit that recognizes, through the input/output terminal, the control command transmitted from the external circuit in a predetermined input cycle; The device further comprises: a readout circuit that reads internal state data of the internal circuit in response to the control command; and an output circuit that outputs the internal state data through the input/output terminal in a predetermined output cycle following the input cycle. It is characterized by:

(Function) The above microprocessor is specially provided with an input/output terminal for outputting internal state data. Inside the microprocessor, a command recognition circuit recognizes control commands received from an external circuit through its input/output terminals. Then, in accordance with this command, the readout circuit reads out the necessary internal state, and the internal state is outputted to the input/output terminal through the output circuit.

In this case, since the input/output terminal is used for bidirectional communication, the input cycle and the output cycle are set in advance at a constant period in a time-sharing manner. Control instructions for input cycles, internal state data for output cycles,
Transfer through input/output terminals. As a result, the internal state data of the microprocessor can be arbitrarily notified using some of the terminals provided in the microprocessor without interfering with the operation of the microprocessor.

(Example) Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is a block diagram of a microprocessor related to the present invention.

In the figure, a large number of terminals 3 are provided on a substrate 2 of a microprocessor 1. Among these terminals 3, one terminal on the lower right, which was not conventionally used for the operation of this microprocessor, is used as an input/output terminal for notification of internal status.
Select a. An external circuit 5 is connected to this input/output terminal 3a through a communication line 4. Further, a display device 6 is connected to the external circuit 5 and displays the internal state of the microprocessor notified through the communication line 4.

On the other hand, this microprocessor is provided with a large number of registers 7, which are used for the operation of the microprocessor, as in the conventional one. The contents of this register 7 correspond to the internal state of this microprocessor 1, and in order to read the internal state data, an instruction recognition circuit 11, an output circuit 12, and a readout circuit 1 are required.
3 are provided.

The command recognition circuit 11 recognizes the external circuit 5 at a predetermined timing.
This is a circuit that recognizes and discriminates control commands input from the communication line 4 and the input/output terminal 3a.

This circuit is comprised of a gate circuit, etc., which reads a control command based on a synchronization signal included in a signal inputted through the input/output terminal 3a, and thereby obtains a control signal for controlling the readout circuit 13.

Further, the read circuit 13 is a circuit that reads internal state data from a predetermined register 7 or all registers 7 in accordance with a control signal output from the instruction recognition circuit 11. This circuit is composed of a gate circuit, etc., which outputs a read control signal to one of the registers in response to a control command, and receives and receives the read signal.

The output circuit 12 is a circuit for sending the internal state data read by the readout circuit 13 from the input/output terminal 3a to the external circuit 5 through the communication line 4. This circuit is composed of a timing control circuit, a gate circuit, etc., which receives the internal state data read out by the readout circuit 13, and serially outputs the internal state data to the communication line 4 based on a synchronization signal. Ru.

Further, the external circuit 5 is composed of, for example, a panel operated by an operator, and is used to input control commands to the communication line 4 at a predetermined timing and to receive internal status data via the communication line 4. .

FIG. 2 is an explanatory diagram of input cycles and output cycles on the communication line 4 when notification of internal status is received from the microprocessor of the present invention.

As shown in the figure, the microprocessor of the present invention uses the input/output terminal 3a (FIG. 1) under time division control in which input cycles and output cycles are alternately arranged. That is, for example, as shown in the figure, in the first input cycle (1), the external circuit 5
(FIG. 1), control commands are input through the input/output terminal 3a (FIG. 1). If this control instruction requests notification of the program status, all internal status data will be transferred to the input/output terminal 3 in the next output cycle 01.
a (FIG. 1) to the external circuit 5 (FIG. 1). In this case, the internal state data for one register may be output in one output cycle, or the output cycle may be set sufficiently long so that, for example, register 7 (first
The internal state data read out from FIG.

In the next input cycle E2, the external circuit 5 (first
Control commands are input from (Fig.). If this requests notification of the internal state of a specific register, the internal state data of the specific register is output in output cycle 02. Below, the same thing applies to the operator's external circuit 5.
The internal state is notified from the microprocessor 1 in a so-called interactive manner. In this case, the microprocessor 1 executes normal arithmetic processing operations in parallel, completely apart from this internal state notification operation.

As shown in Fig. 2, if an input cycle and an output cycle are provided at regular intervals, and thereby the input of control commands and the output of internal state data are performed in a time-sharing manner, one This process can be executed using only input/output terminals, and it is also easy to recognize control commands and control the output timing of internal state data.

That is, in the circuit shown in FIG. 1, first, in an input cycle, when a control command is input from the external circuit 5 to the command recognition circuit 11, the command recognition circuit 11 recognizes the control command as, for example, notifying the program status. Recognize it as a command. A control signal is sent to the readout circuit 13 based on the recognition result, and the readout circuit 13 sequentially switches registers 7 from which internal state data should be read, and transfers the internal state to the output circuit 12. The output circuit 12 outputs the read internal state data to the input/output terminal 3a in time with the start of the output cycle.

Note that the microprocessor according to the present invention can have not only the function of reading internal state data but also the function of controlling the operation of the microprocessor itself, changing the internal state, etc.

Hereinafter, the control commands input from the external circuit 5 to the microprocessor 1 will be specifically explained using an example.

FIG. 3 is a list showing the relationship between the functions of this microprocessor and input/output cycles.

First, when executing the CPU stop function, for example, a control command "O○゛°" is input in the input cycle. In this case, the microprocessor l immediately stops normal arithmetic operations, and nothing is output in the output cycle. .

In the next CPU reset function, the control command is set to, for example, '01', and when this is input, the microprocessor is initialized. Of course, in this case as well, nothing is output in the output cycle.

Next, in the register control function, when a read function is executed, the control command is e.g.
IOH" and the register number is input in the next input cycle. In response, the microprocessor outputs the contents of that register in the output cycle.

Next, in the register control function, when executing the write function, the control command in the input cycle is, for example, “”
IIH", and the register number is input in the next input cycle. Then, when a register value is input in the next input cycle, it is input to the register with the previously designated register number. in this case,
Nothing is output during the output cycle. In this way,
The contents of registers inside the microprocessor are also rewritten.

Next, in the memory content control function, when executing the read function, the control command is inputted as, for example, "20H", the memory address is inputted in the next input cycle, and the number of bytes is inputted in the next input cycle. do. As a result, the memory contents are output from the microprocessor during the output cycle. That is, in this case, the microprocessor can execute processing such as reading the contents of a memory connected to the microprocessor and notifying an external circuit.

Next, in the write function of the in-memory control function, input the control command, for example, "'21H", input the memory address in the next input cycle, input the number of bytes in the next input cycle, and input the last Input the memory setting value in the input cycle.

As a result, the memory setting value is written to the corresponding memory. In this case, nothing is output during the output cycle. Thus, in this embodiment, control instructions are input to the microprocessor in a combined set of instructions, each using one or more input cycles. On the microprocessor 1 side, the instruction recognition circuit 11 shown in FIG. 1 performs a known instruction decoding process, recognizes this instruction, and executes an operation corresponding to the instruction.

Next, regarding the I10 boat control function, when executing its read function, the control command is set to, for example, "30H", the I10 boat is specified in the next input cycle, and the address is specified in the next input cycle, Specify the number of bytes on the next input cycle. This causes the internal state data of the various I10 ports accessed by the microprocessor to be output in the output cycle.

In addition, in the case of the write function in the I10 boat control function, the control command is, for example, 31H''', the I10 boat is specified in the next input cycle, the address is specified in the next input cycle, and the address is specified in the next input cycle. Specify the number of bytes and specify the vote value on the last input cycle.This will write the vote value for the given I10 vote.In this case, nothing will be output on the output cycle.

Next, in the case of the execution command notification function, the control command is input as '40H' in the execution command notification function.In this case, the address being executed and the contents of the command are output in the output cycle.

Furthermore, in the execution command notification function, for the data notification function that is being accessed, a control command, for example, "41H" is input. In this case, in the output cycle, the address being accessed, the read/write type, and its access value are output.

In addition, regarding this execution command notification, since a large amount of internal state data is outputted, the output cycle is repeatedly used two to three times or more.

For the final status read function, there are no input cycles. That is, for example, in the case of the microprocessor of this embodiment, if no instruction is given in the input cycle, all of the microprocessor's The system has a configuration in which internal state data is output in a predetermined order.Using these functions, it is possible to not only notify the internal state, but also rewrite the contents of registers, etc., or control the operation of the microprocessor itself, as necessary. , extremely complex control becomes possible.

The present invention is not limited to the above embodiments.

In the embodiment, an example was shown in which one terminal of the microprocessor is used to input control commands and output internal state data, but if there is sufficient number of terminals, two or more terminals can be used. There is no problem if you use it to do this. Further, the above circuit configuration added inside the microprocessor may be replaced with various circuits having similar functions.

(Effects of the Invention) Since the microprocessor of the present invention described above incorporates a circuit for notifying the internal state, it is not necessary to externally attach a dedicated chip such as an emulator when notifying the internal state. There is no sex.

Furthermore, since notification of the internal state of the microprocessor can be performed in parallel with the normal arithmetic processing of the microprocessor, real-time notification of the internal state is possible without affecting the operation of the microprocessor.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the microprocessor according to the present invention, Fig. 2 is an explanatory diagram of its input cycle and output cycle, and Fig. 3 is an example of the functions and input/output cycle of the microprocessor of the present invention. This is a list showing. l...microprocessor, 2...board, 3...
Terminal, 3a... Input/output terminal, 4... Communication line, 5...
・External circuit, 6... Display device, 7... Register, 1
1... Command recognition circuit, 12... Output circuit, 13...
・Readout circuit. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] Provided separately from normal arithmetic processing data input/output terminals,
an input/output terminal for inputting a control command from an external circuit during the normal arithmetic processing operation and outputting internal state data in response to the control command; a command recognition circuit that recognizes the input control command through the input/output terminal; a readout circuit that reads internal state data of the internal circuit in accordance with the control command; A microprocessor comprising: an output circuit that outputs internal state data through the input/output terminal.