JPH03103632U - - Google Patents
Info
- Publication number
- JPH03103632U JPH03103632U JP1100590U JP1100590U JPH03103632U JP H03103632 U JPH03103632 U JP H03103632U JP 1100590 U JP1100590 U JP 1100590U JP 1100590 U JP1100590 U JP 1100590U JP H03103632 U JPH03103632 U JP H03103632U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- source
- switch
- rise
- input impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は第１図の動作説明図、第３図は第１図の回路
の応用例を示す回路図、第４図はＦＥＴスイツチ
の等価回路、第５図は第４図の動作説明図である
。
１……スイツチ（ＦＥＴ）、２……入力端子、
３……制御端子、４……アンプ（演算増幅器）、
５……出力端子、６……高入力インピーダンスバ
ツフア（演算増幅器）、Ｒ……抵抗、Ｃ１〜Ｃ３
……コンデンサ。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a diagram explaining the operation of Figure 1, Figure 3 is a circuit diagram showing an application example of the circuit in Figure 1, Figure 4 is an equivalent circuit of a FET switch, and Figure 5 is a diagram explaining the operation of Figure 4. . 1...Switch (FET), 2...Input terminal,
3...Control terminal, 4...Amplifier (operational amplifier),
5...Output terminal, 6...High input impedance buffer (operational amplifier), R...Resistance, C1 to C3
...Capacitor.
Claims (1)
ＯＦＦ信号の速い立ち上がりを緩やかな立ち上が
りに整形する波形整形回路と、 前記ＦＥＴのソース、ドレイン間及びソース、
ゲート間に接続された電圧分割用コンデンサと、 前記ＦＥＴのソースに接続された高入力インピ
ーダンスを有するバツフア、 とで構成されたことを特徴とするＦＥＴスイツチ
。[Scope of claim for utility model registration] FET, connected to the gate of the FET, and a switch ON/OFF
a waveform shaping circuit that shapes a fast rise of an OFF signal into a slow rise; a source, a drain and a source of the FET;
A FET switch comprising: a voltage dividing capacitor connected between the gates; and a buffer having high input impedance connected to the source of the FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1100590U JPH03103632U (en) | 1990-02-06 | 1990-02-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1100590U JPH03103632U (en) | 1990-02-06 | 1990-02-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03103632U true JPH03103632U (en) | 1991-10-28 |
Family
ID=31514549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1100590U Pending JPH03103632U (en) | 1990-02-06 | 1990-02-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03103632U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014042146A (en) * | 2012-08-22 | 2014-03-06 | Denso Corp | Power circuit and drive circuit |
-
1990
- 1990-02-06 JP JP1100590U patent/JPH03103632U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014042146A (en) * | 2012-08-22 | 2014-03-06 | Denso Corp | Power circuit and drive circuit |
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