JPH0310397U - - Google Patents
Info
- Publication number
- JPH0310397U JPH0310397U JP7052989U JP7052989U JPH0310397U JP H0310397 U JPH0310397 U JP H0310397U JP 7052989 U JP7052989 U JP 7052989U JP 7052989 U JP7052989 U JP 7052989U JP H0310397 U JPH0310397 U JP H0310397U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- ram
- output
- cpu
- static ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003068 static effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Dram (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7052989U JPH0310397U (2) | 1989-06-15 | 1989-06-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7052989U JPH0310397U (2) | 1989-06-15 | 1989-06-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0310397U true JPH0310397U (2) | 1991-01-31 |
Family
ID=31606752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7052989U Pending JPH0310397U (2) | 1989-06-15 | 1989-06-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0310397U (2) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5928015U (ja) * | 1982-08-17 | 1984-02-21 | 日本ケ−ス株式会社 | 包装箱 |
-
1989
- 1989-06-15 JP JP7052989U patent/JPH0310397U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5928015U (ja) * | 1982-08-17 | 1984-02-21 | 日本ケ−ス株式会社 | 包装箱 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR910005174A (ko) | 이중영역 기억장치 제어기 및 그 제어방법 | |
| JPH0310397U (2) | ||
| JPS6215199U (2) | ||
| ATE242900T1 (de) | Verfahren, system und rechnerprogramm für das überlappen und übertragen von graphischen daten mit einem einzelnen prozessor | |
| JPS6273494A (ja) | ランダムアクセスメモリ制御装置 | |
| JPS60640U (ja) | Dma処理とプログラム計測モ−ドの並行処理システム | |
| JPS61137294A (ja) | メモリ集積回路 | |
| KR940007285Y1 (ko) | Vme 인터페이스버스 메모리보드의 디램 사이클 아비트레이션 로직 | |
| JPH02145447U (2) | ||
| JPH01120251U (2) | ||
| KR860002760A (ko) | Z 80 cpu의 시스템 프로그램 보호회로 | |
| JPH0196047U (2) | ||
| JPS63144494A (ja) | メインメモリ−のリフレツシユ方式 | |
| JPS5442944A (en) | Refresh address control system for memory | |
| JPS6338195U (2) | ||
| JPH06103766A (ja) | Dramリフレッシュアービタ回路 | |
| JPS62134134U (2) | ||
| JPS61162160U (2) | ||
| JPH0255341U (2) | ||
| JPS5396640A (en) | Memory control system | |
| JPS62166540U (2) | ||
| JPS59164335U (ja) | パルス発生装置 | |
| JPH0255346U (2) | ||
| JPH022751U (2) | ||
| JPS6085441U (ja) | 位相反転クロツク発生回路 |