JPH03104756U - - Google Patents
Info
- Publication number
- JPH03104756U JPH03104756U JP1990013128U JP1312890U JPH03104756U JP H03104756 U JPH03104756 U JP H03104756U JP 1990013128 U JP1990013128 U JP 1990013128U JP 1312890 U JP1312890 U JP 1312890U JP H03104756 U JPH03104756 U JP H03104756U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin
- sealed
- lead
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990013128U JPH03104756U (sr) | 1990-02-15 | 1990-02-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990013128U JPH03104756U (sr) | 1990-02-15 | 1990-02-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104756U true JPH03104756U (sr) | 1991-10-30 |
Family
ID=31516562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990013128U Pending JPH03104756U (sr) | 1990-02-15 | 1990-02-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104756U (sr) |
-
1990
- 1990-02-15 JP JP1990013128U patent/JPH03104756U/ja active Pending