JPH0310502U - - Google Patents
Info
- Publication number
- JPH0310502U JPH0310502U JP7134689U JP7134689U JPH0310502U JP H0310502 U JPH0310502 U JP H0310502U JP 7134689 U JP7134689 U JP 7134689U JP 7134689 U JP7134689 U JP 7134689U JP H0310502 U JPH0310502 U JP H0310502U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrodes
- layer
- glass layer
- chip resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Description
第１図は本考案の原理図、第２図は本考案の各
実施例の構成図、第３図は従来のチツプ抵抗の構
成図、第４図は従来のチツプ抵抗の実装状態図で
ある。
図中、１……セラミツク基板、２……電極、３
……抵抗層、４……オーバコートガラス層、４Ａ
……その端部、７……半田、７Ａ……フイレツト
である。
Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a block diagram of each embodiment of the present invention, Fig. 3 is a block diagram of a conventional chip resistor, and Fig. 4 is a diagram of the mounting state of a conventional chip resistor. . In the figure, 1...ceramic substrate, 2...electrode, 3
...Resistance layer, 4...Overcoat glass layer, 4A
. . . its end, 7 . . . solder, 7A . . . fillet.
Claims (1)
た電極２と、 該基板の表面に形成され、両端部が該電極に接
続された抵抗層３と、 該抵抗層の表面を覆うオーバコートガラス層４
とを備え、 該ガラス層の端部４Ａを前記電極上において波
型に形成してなることを特徴とするチツプ抵抗。[Claims for Utility Model Registration] A ceramic substrate 1, electrodes 2 formed on both ends of the substrate from the top to the bottom, and a resistive layer 3 formed on the surface of the substrate, both ends connected to the electrodes. , an overcoat glass layer 4 covering the surface of the resistance layer
A chip resistor comprising: an end portion 4A of the glass layer formed in a wave shape on the electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7134689U JPH0310502U (en) | 1989-06-19 | 1989-06-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7134689U JPH0310502U (en) | 1989-06-19 | 1989-06-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0310502U true JPH0310502U (en) | 1991-01-31 |
Family
ID=31608289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7134689U Pending JPH0310502U (en) | 1989-06-19 | 1989-06-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0310502U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017126593A (en) * | 2016-01-12 | 2017-07-20 | パナソニックＩｐマネジメント株式会社 | Chip resistor |
| JP2018139248A (en) * | 2017-02-24 | 2018-09-06 | パナソニックＩｐマネジメント株式会社 | Chip resistor mounting structure |
-
1989
- 1989-06-19 JP JP7134689U patent/JPH0310502U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017126593A (en) * | 2016-01-12 | 2017-07-20 | パナソニックＩｐマネジメント株式会社 | Chip resistor |
| JP2018139248A (en) * | 2017-02-24 | 2018-09-06 | パナソニックＩｐマネジメント株式会社 | Chip resistor mounting structure |