JPH0310537U - - Google Patents
Info
- Publication number
- JPH0310537U JPH0310537U JP1989071910U JP7191089U JPH0310537U JP H0310537 U JPH0310537 U JP H0310537U JP 1989071910 U JP1989071910 U JP 1989071910U JP 7191089 U JP7191089 U JP 7191089U JP H0310537 U JPH0310537 U JP H0310537U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- solder bumps
- circuit board
- mounting position
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
第１図ａは本考案におけるＩＣ取付け位置目安
パターンを設けた回路基板上のパターン配線平面
図、第１図ｂは半田バンプ付ＩＣを本考案の回路
基板に実装した平面図、第１図ｃは第１図ｂのＡ
−Ａ断面図、第２図ａは従来の回路基板のパター
ン配線平面図、第２図ｂは従来の回路基板に半田
バンプ付ＩＣを実装し、位置ズレを発生しシヨー
ト状態となつている例を示した平面図、第２図ｃ
は第２図ｂのＢ−Ｂ断面図である。
１……ＩＣ取付け位置目安パターン、２……シ
ヨートされている配線パターン、３……独立した
配線パターン、４……半田バンプ付ＩＣ、５……
ガラエポ回路基板、６……半田バンプ。
Figure 1a is a plan view of the pattern wiring on a circuit board provided with the IC mounting position guide pattern of the present invention, Figure 1b is a plan view of an IC with solder bumps mounted on the circuit board of the present invention, and Figure 1c. is A in Figure 1b
-A sectional view, Figure 2a is a pattern wiring plan view of a conventional circuit board, and Figure 2b is an example of an IC with solder bumps mounted on a conventional circuit board, resulting in positional deviation and short status. Plan view showing , Figure 2c
is a sectional view taken along line B-B in FIG. 2b. 1...IC mounting position guide pattern, 2...Shooted wiring pattern, 3...Independent wiring pattern, 4...IC with solder bumps, 5...
Gala Epo circuit board, 6...solder bumps.
Claims (1)
数本あるパターン配線を有するガラエポ回路基板
形状において、半田バンプ付ＩＣの取付位置目安
パターンを設けたことを特徴とするガラエポ回路
基板のパターン形状。 A pattern shape of a glass epoxy circuit board having a wiring pattern including a plurality of input terminals or output terminals of an IC with solder bumps, characterized in that a pattern is provided as a reference pattern for the mounting position of an IC with solder bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989071910U JPH0310537U (en) | 1989-06-19 | 1989-06-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989071910U JPH0310537U (en) | 1989-06-19 | 1989-06-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0310537U true JPH0310537U (en) | 1991-01-31 |
Family
ID=31609369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989071910U Pending JPH0310537U (en) | 1989-06-19 | 1989-06-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0310537U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50152766U (en) * | 1975-02-10 | 1975-12-18 | ||
| JPS523767U (en) * | 1975-06-24 | 1977-01-11 | ||
| JP2014132682A (en) * | 2014-03-14 | 2014-07-17 | Renesas Electronics Corp | Resin encapsulated semiconductor device manufacturing method |
| USRE45931E1 (en) | 1999-11-29 | 2016-03-15 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device |
-
1989
- 1989-06-19 JP JP1989071910U patent/JPH0310537U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50152766U (en) * | 1975-02-10 | 1975-12-18 | ||
| JPS523767U (en) * | 1975-06-24 | 1977-01-11 | ||
| USRE45931E1 (en) | 1999-11-29 | 2016-03-15 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device |
| JP2014132682A (en) * | 2014-03-14 | 2014-07-17 | Renesas Electronics Corp | Resin encapsulated semiconductor device manufacturing method |