JPH0310672U - - Google Patents

Info

Publication number
JPH0310672U
JPH0310672U JP6937689U JP6937689U JPH0310672U JP H0310672 U JPH0310672 U JP H0310672U JP 6937689 U JP6937689 U JP 6937689U JP 6937689 U JP6937689 U JP 6937689U JP H0310672 U JPH0310672 U JP H0310672U
Authority
JP
Japan
Prior art keywords
circuit
format
selection
video signal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6937689U
Other languages
Japanese (ja)
Other versions
JPH0731646Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989069376U priority Critical patent/JPH0731646Y2/en
Publication of JPH0310672U publication Critical patent/JPH0310672U/ja
Application granted granted Critical
Publication of JPH0731646Y2 publication Critical patent/JPH0731646Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Color Television Systems (AREA)
  • Television Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示す構成図、第
2図は方式変換回路の構成図、第3図はNTSC
方式からPAL方式への走査線変換の説明図、第
4図はEVFの偏向回路の要部構成図、第5図は
垂直偏向電流の波形図、第6図は日付表示の説明
図、第7図はPAL方式からNTSC方式への走
査線変換の説明図である。 41……撮像素子、43……プロセス回路、4
6……エンコーダ、48,51……切換スイツチ
、49……方式変換回路、52……コントローラ
、53……NTSC方式/PAL方式切換キー、
55……電子ビユーフアインダ、58……ライン
出力端子、59……日付回路、61……日付挿入
キー。
Figure 1 is a configuration diagram showing an embodiment of this invention, Figure 2 is a configuration diagram of a system conversion circuit, and Figure 3 is an NTSC
An explanatory diagram of scanning line conversion from system to PAL system, Fig. 4 is a main part configuration diagram of the EVF deflection circuit, Fig. 5 is a waveform diagram of vertical deflection current, Fig. 6 is an explanatory diagram of date display, Fig. 7 The figure is an explanatory diagram of scanning line conversion from PAL system to NTSC system. 41...Image sensor, 43...Process circuit, 4
6... Encoder, 48, 51... Changeover switch, 49... System conversion circuit, 52... Controller, 53... NTSC system/PAL system switching key,
55...Electronic viewfinder, 58...Line output terminal, 59...Date circuit, 61...Date insertion key.

Claims (1)

【実用新案登録請求の範囲】 (1) 一の方式の映像信号が供給される方式変換
回路と、 上記一の方式の映像信号および上記方式変換回
路より出力される他の方式の映像信号のいずれか
を選択して出力する選択回路とを備えるビデオカ
メラ。 (2) 一の方式の映像信号が供給される方式変換
回路と、 上記一の方式の映像信号および上記方式変換回
路より出力される他の方式の映像信号のいずれか
を選択して出力する選択回路とを備えるビデオカ
メラにおいて、 上記選択回路の出力信号が供給される表示器が
設けられ、上記選択回路の選択に応じて上記表示
器の回路系の切り換えが行なわれることを特徴と
するビデオカメラ。 (3) 一の方式の映像信号が供給される方式変換
回路と、 上記一の方式の映像信号および上記方式変換回
路より出力される他の方式の映像信号のいずれか
を選択して出力する選択回路とを備えるビデオカ
メラにおいて、 上記選択回路の出力信号に挿入される日付表示
信号を出力する日付回路が設けられ、上記選択回
路の選択に応じて上記日付回路からの日付表示信
号の出力タイミングの切り換えが行なわれること
を特徴とするビデオカメラ。
[Claims for Utility Model Registration] (1) A system conversion circuit to which a video signal of one system is supplied, and any of the video signal of the above one system and the video signal of another system outputted from the system conversion circuit. and a selection circuit that selects and outputs a video camera. (2) A format conversion circuit to which a video signal of one format is supplied; and a selection of selecting and outputting either the video signal of the first format or the video signal of another format output from the format conversion circuit. A video camera comprising: a display device to which an output signal of the selection circuit is supplied, and a circuit system of the display device is switched in accordance with a selection of the selection circuit. . (3) A format conversion circuit to which a video signal of one format is supplied; and a selection of selecting and outputting either the video signal of the first format or the video signal of another format output from the format conversion circuit. A video camera is provided with a date circuit that outputs a date display signal to be inserted into the output signal of the selection circuit, and the output timing of the date display signal from the date circuit is adjusted according to the selection of the selection circuit. A video camera characterized by switching.
JP1989069376U 1989-06-14 1989-06-14 Video camera Expired - Fee Related JPH0731646Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989069376U JPH0731646Y2 (en) 1989-06-14 1989-06-14 Video camera

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989069376U JPH0731646Y2 (en) 1989-06-14 1989-06-14 Video camera

Publications (2)

Publication Number Publication Date
JPH0310672U true JPH0310672U (en) 1991-01-31
JPH0731646Y2 JPH0731646Y2 (en) 1995-07-19

Family

ID=31604626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989069376U Expired - Fee Related JPH0731646Y2 (en) 1989-06-14 1989-06-14 Video camera

Country Status (1)

Country Link
JP (1) JPH0731646Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60150853U (en) * 1984-03-17 1985-10-07 キヤノン株式会社 Imaging device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60150853U (en) * 1984-03-17 1985-10-07 キヤノン株式会社 Imaging device

Also Published As

Publication number Publication date
JPH0731646Y2 (en) 1995-07-19

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Legal Events

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LAPS Cancellation because of no payment of annual fees