JPH03107828U - - Google Patents
Info
- Publication number
- JPH03107828U JPH03107828U JP1541990U JP1541990U JPH03107828U JP H03107828 U JPH03107828 U JP H03107828U JP 1541990 U JP1541990 U JP 1541990U JP 1541990 U JP1541990 U JP 1541990U JP H03107828 U JPH03107828 U JP H03107828U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- oscillation circuit
- voltage
- oscillator
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第1図はこの考案の実施例である位相同期発振
回路を示すブロツク図、第2図は従来の位相同期
発振回路の例を示すブロツク図である。
1……入力端子、2……分周器、3……位相比
較器、4……ループフイルタ、5……電圧制御発
振器、6……プリスケーラ、7……モジユールコ
ントロール付き分周器、8……出力端子、9……
電圧ホールド回路、10……電圧制御水晶発振器
、11……分周器、12……位相比較器、13…
…ループフイルタ、14……電圧制御発振器、1
5……分周器、16……出力端子、17……第1
の発振回路、18……第2の発振回路。
FIG. 1 is a block diagram showing a phase-locked oscillation circuit as an embodiment of this invention, and FIG. 2 is a block diagram showing an example of a conventional phase-locked oscillation circuit. 1... Input terminal, 2... Frequency divider, 3... Phase comparator, 4... Loop filter, 5... Voltage controlled oscillator, 6... Prescaler, 7... Frequency divider with module control, 8 ...Output terminal, 9...
Voltage hold circuit, 10... Voltage controlled crystal oscillator, 11... Frequency divider, 12... Phase comparator, 13...
...Loop filter, 14...Voltage controlled oscillator, 1
5... Frequency divider, 16... Output terminal, 17... First
oscillation circuit, 18... second oscillation circuit.
Claims (1)
振する電圧制御水晶発振器を有する第1の発振回
路と、第1の発振回路の出力信号に対して位相同
期ループを形成して発振する電圧制御発振器を有
する第2の発振回路とで構成され、第1の発振回
路のループフイルタと電圧制御水晶発振器の間に
、ホールド信号オフ時には入力をそのまま出力し
ホールド信号オン時に直前の出力をホールドする
ホールド回路を介在させたことを特徴とする位相
同期発振回路。 a first oscillation circuit including a voltage-controlled crystal oscillator that oscillates by forming a phase-locked loop with respect to a reference signal; and a voltage-controlled oscillator that oscillates by forming a phase-locked loop with respect to an output signal of the first oscillation circuit. A hold circuit is provided between the loop filter of the first oscillation circuit and the voltage controlled crystal oscillator, and outputs the input as is when the hold signal is off, and holds the previous output when the hold signal is on. A phase synchronized oscillator circuit characterized by interposing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1541990U JPH03107828U (en) | 1990-02-19 | 1990-02-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1541990U JPH03107828U (en) | 1990-02-19 | 1990-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03107828U true JPH03107828U (en) | 1991-11-06 |
Family
ID=31518724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1541990U Pending JPH03107828U (en) | 1990-02-19 | 1990-02-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03107828U (en) |
-
1990
- 1990-02-19 JP JP1541990U patent/JPH03107828U/ja active Pending
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