JPH03110637A - Instruction trace system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a processor to which a microprogram control method is applied and which is capable of a multiprocessor configuration, and particularly to a processor for exclusive control between processors. The present invention relates to an instruction tracing method for tracing instructions that require setting of a test and set (TAS) flag.

(Prior Art) In a system with a multiprocessor configuration (multiprocessor system), a plurality of processors (arithmetic control unit, hereinafter referred to as ACP) may operate the same area on memory. At this time, it is necessary to perform exclusive control between ACPs so that processing in each ACP is executed correctly.

In order to perform this exclusive control efficiently, the ACP generally supports a memory ink clock and an interlock function between instructions. In other words, in a microprogram controlled ACP, the TAS (TAS controlled by the microprogram) can be operated by the microprogram of each ACP.
A flag (hereinafter referred to as μTAS flag) is provided for the μTAS flag (hereinafter referred to as μTAS flag), and when the μTAS flag is in the reset state, the flag is set (this is referred to as μTAS set or μTAS acquisition). After performing this, an instruction process for manipulating the above area on the memory is started, and after the process is completed, the μTAS flag is reset, thereby realizing exclusive control of instructions between ACPs.

(Problem to be Solved by the Invention) In the above-mentioned microprocessor system, when control of microinstructions is disrupted due to a microprogram error, hardware failure, etc., one ACP becomes a μTA.
You may end up in a state where you have acquired S. Conventionally, in order to prevent such a situation from occurring, the acquisition time of μTAS was monitored, and when a certain period of time was exceeded, a failure (μTAS) was detected.
AS stall error). However, this was the trigger for the μTAS stall error (
In other words, program processing continues between the execution of the instruction (which required μTAS acquisition) and the detection of the error, so it is difficult to find out which instruction caused the error. The problem with the instruction tracing method is that it is extremely difficult.

This invention was made in view of the above circumstances, and its purpose is to analyze errors in the event of a failure (μTAS stall error) in which one processor leaves the μTAS flag (test and set flag) set. The purpose of the present invention is to provide an instruction tracing method that can be easily performed.

[Structure of the Invention] (Means for Solving the Problems) This invention provides TAS (
In a multiprocessor system, exclusive control of instructions (macro instructions) between processors is performed by operating the TAS acquisition timing (μTAS set timing). Instructions that required TAS acquisition (macro instructions) were provided with an instruction trace means to retain the instruction information at that time.
This feature is characterized by selectively tracing only the information of.

(Operation) According to the above configuration, only the information of the instruction that required TAS acquisition can be traced, so even if a failure (μτAS stall error) is detected after a certain period of time has passed after TAS acquisition, the execution of any instruction Error analysis, such as whether or not a failure occurred, can be easily performed.

(Embodiment) Hereinafter, a case where an embodiment of the present invention is applied to a multiprocessor system including four processors will be described with reference to the drawings.

FIG. 1 is a block diagram of a processor (ACP) that applies a microprogram control system and is capable of multiprocessor configuration, and is a block diagram of a part related to the present invention.
1 is a block configuration diagram of a part related to the present invention of a multiprocessor system equipped with a multiprocessor system; FIG.

In Figure 2, 10-1-10-4 is ACP,
Each has a μTAS control unit 11 for performing exclusive control between ACPs. In this embodiment, the priority of exclusive control between ACPs is highest for A CP 10-1, followed by A CP to-2, A CP to-8, and ACP
The order is lo-4. The μTAS control unit 11 includes a flip-flop (hereinafter referred to as μTAS F/F) 2 used as a μTAS flag for exclusive control.
1, and a gate circuit 22 for controlling the setting operation for this μTAS F/F 21. The μTAS F/F 21 is set by a valid output signal from the gate circuit 22 to indicate the μTAS acquisition status.
In addition to outputting a TAS acquisition signal 12, the ACP is reset by a valid μTAS reset request signal 13 generated within its own ACP. The gate circuit 22 also receives a μTAS set request signal 1 generated within its own ACP.
4, μ generated in an ACP with higher priority than itself
TAS set request “signal 14, and μT in each ACP
Depending on the state of μTAS signal 24 (true at °0゛) indicating whether any of ASF/F21 is set or not, μ
It is designed to set TAS F/F21.

A CP 10-1 to 10-4 are system control units (hereinafter referred to as SCU) 2 that control the entire system.
5 is connected. This 5CU 25 is provided with a stall monitoring device 2B that monitors the period during which the μTAS signal 24 is constant (“0”) and generates an error (μTAS stall error) interrupt when a predetermined time is exceeded. There is.

Next, A CP 10-1 (i-1 to 4
) is explained below. In the figure, 15 is a microprogram memory in which various microprograms are stored;
A decoder 1B decodes the contents of the command field of the microinstruction read from the microprogram memory 15 and outputs various control signals such as the μTAS set request signal 14 or the μTAS reset request signal 13.
A decoder (DEC) 17 decodes the contents of the bus control field of a microinstruction read from the microprogram memory 1B and outputs various control signals related to bus control, such as an output control signal OE for controlling a bus driver 20, which will be described later. ).

Reference numeral 18 denotes an instruction trace circuit (hereinafter referred to as the μTAS trace circuit) for tracing information on the executing instruction, such as location information (contents of a location counter), regarding the executed instruction at the time of μTAS acquisition. The μTAS trace circuit 18 is a
A holding means, for example, a register (hereinafter referred to as μTAS trace register) for holding information on the instruction being executed in response to the TAS acquisition signal 12, and an output control signal from the decoder 17 to output the contents held in the μTAS trace register 19. Internal bus BU of A CP 10-1 according to OE
It has a bus driver 20 that outputs to S.

Next, the operation of an embodiment of the present invention will be described in order: (1) Exclusive control of μTAS, (2) μTAS stall error detection, (2) μTAS race.

■Exclusive control of μTAS First, in A CP 10-1 (i-1 to 4), A
When executing an instruction that requires exclusive control between CPs, the first
From the microprogram memory 15 shown in the figure, μTAS
A microinstruction for requesting a set (μTAS set request microinstruction) is read. The decoder 1B decodes the contents of the command field of the microinstruction read from the microprogram memory 15, and if the microinstruction is a μTAS set request microinstruction, the active μTAS set request signal 14 of logic “1” is activated. Output. Now, μTA with a certain A CP to-1
When the S set request signal 14 is generated, other ACP's (
If none of the μTAS F/Fs (in the μTAS control unit 11) are set (however, if the μTAS F/F of its own
F/F21 is also not set), μ
The TAS signal 24 becomes '1# (false).

When the active μTAS set request signal 14 is generated, the μTAS control unit control circuit 22 of the A CP 10-1 determines that the μTAS signal 24 is “al” and the own A
Only when the active μTAS set request signal 14 is not output from the ACP, which has a higher priority for acquiring μTAS than the CP, the active signal is sent to the μTAS F/F2.
Output to the set terminal (J input) of 1, μTAS F/
Set F21. This allows μTAS F/F
Active μTA with logic “1” from (Q output of)
The S acquisition signal 12 is output, and the A CP 10-1 is μT.
Obtain AS. When ACPlo-1 acquires μTAS, it moves to instruction processing that requires the above-mentioned exclusive control. Also, by setting μTASF/F 21, μTAS signal 24 becomes “0” (true), and other AC
μTAS acquisition from P is prohibited.

Eventually, when the above instruction processing is completed, A-CPlo-1
A microinstruction for requesting a μTAS reset (μTAS reset request microinstruction) is read from the microprogram memory 15 in the microcontroller. In this case, the decoder 16 outputs an active μTAS reset request signal I3 of logic “1°.This μTAS reset request signal 13
It is supplied to the reset terminal (K input) of /F21, thereby resetting μTASF/F21. A
CP 1O-1(7) μT A SF / F 21
is reset, (μTAS F/F of other ACP
21 have all been reset), the μTAS signal 24 returns to “1” (because), and the μTAS signal 24 from other ACPs
It becomes possible to obtain AS.

■μTAS stall error detection The μTAS signal 24 described above is also supplied to the stall monitoring device 26 of the 5CU 25. The stall monitoring device 26 is
Time monitoring is started from the time when the μTAS signal 24 becomes "Om", and it is checked whether this state of "0" continues for a predetermined period of time or more.

If the μTAS reset request microinstruction is not issued correctly due to a microprogram error, or if the μTAS
Due to factors such as AS F/F21 failure, μT A
If the SF/F 21 remains set and the μTAS signal 24 remains in the “0#” state for a certain period of time, the stall monitoring device 26
Assuming that a stall error has occurred, a μTAS stall error interrupt is generated.

■μTAS) Race As mentioned above, the stall monitoring device 2G
An AS stall error is detected after a certain period of time has elapsed after the μTAS F/F 21 was set upon execution of an instruction requiring μTAS acquisition. Therefore, even if the instruction processing of the ACP 10-1 progresses during this time and a μTAS stall error interrupt occurs, it is difficult to check which instruction was executed when the μTAS stall error occurred. Therefore, in this embodiment, as shown in FIG. 1, a μTAS trace circuit 18 is provided in the A CP 10-1, and as described below, information on instructions that require μTAS acquisition is reliably traced. There is. That is, in this embodiment, a μTAS trace register 19 having a load enable terminal LE to which the μTAS acquisition signal 12 is supplied is provided in the μTAS trace circuit 18, and when the μTAS acquisition signal 12 becomes active, Information on the currently executing command (information such as the contents of the location counter) is loaded into the register 19. As described above, the μTAS acquisition signal 12 is transmitted to the μTASF/μTAS in the μTAS control unit 11 in response to the μTAS set request signal 14 generated by microprogram control during execution of an instruction requiring μTAS acquisition.
It becomes active when F21 is set. Therefore, by loading the instruction information at that time into the μTAS trace register 19 according to the μTAS acquisition signal 12, the instruction information at the time of μTAS acquisition (i.e., μ
Information on instructions that required TAS acquisition) is reliably transferred to μTAS.
) can be traced to race register 19. The contents of the .mu.TAS register 19 are normally updated to the instruction information (2) each time a new .mu.TAS is acquired.

Now, when a μTAS error is detected in the stall monitoring device 2B and a μTAS stall error interrupt occurs, error analysis processing is performed in the ACP 10-1.

In this error analysis process, μTAS trace register 1
A transfer microinstruction is executed that specifies 9 as the source. In this case, an active output control signal OE is output from the decoder 17 in accordance with (the contents of the bus control field of) the transfer microinstruction described above. When the output control signal OE becomes active, the bus driver 20 enters the output enable state. As a result, μTAS) race register 1
The instruction information when the most recent μTAS was acquired, which was traced to
S and sent for error analysis.

Note that in the above embodiment, the μTAS trace register 19
Although we have explained the case where one register 19 is provided,
Similarly, it is also possible to perform n-level tracing by connecting n registers that are load enabled in response to the μTAS acquisition signal 12 in multiple stages.

[Effects of the Invention] As described in detail above, according to the present invention, each processor of a microprocessor system is provided with an instruction tracing means for retaining instruction information at the TAS acquisition timing, thereby eliminating the need for TAS acquisition. Since we selectively trace only information about instructions (macro instructions) that have been executed, even if a failure (μTAS stall error) is detected after a certain amount of time has passed after TAS acquisition, it will be possible to trace the failure at any instruction execution time. Error analysis such as errors can be easily performed.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and FIG. 1 is a block diagram of a processor (ACP) that applies a microprogram control system and is capable of multiprocessor configuration, and FIG. 2 is a block diagram of a portion related to the present invention. 1 is a block diagram of a portion of a multiprocessor system including a plurality of processors related to the present invention; FIG. 10-1 to 10-4.10-1... Processor (AC
P), 11...μTAS control unit, 12...μTAS
Acquisition signal, 13... μTAS reset request signal, 14
...μTAS set request signal, 15...micro program memory, 1g...μTAS) race circuit, I
9...μTAS) race register, 21...μTA
S F/F, 26... Stall monitoring device.

Claims (1)

[Scope of Claims] In a multiprocessor system including a plurality of processors and in which a test and set (TAS) operation is performed by microprogram processing for exclusive control among the processors, each of the processors is provided with a test and set (TAS) operation.・Instruction tracing characterized by providing an instruction tracing means for holding instruction information at the set acquisition timing, and selectively tracing only the information of the instruction that required test and set acquisition. method.