JPH03111073U - - Google Patents

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Publication number
JPH03111073U
JPH03111073U JP2012890U JP2012890U JPH03111073U JP H03111073 U JPH03111073 U JP H03111073U JP 2012890 U JP2012890 U JP 2012890U JP 2012890 U JP2012890 U JP 2012890U JP H03111073 U JPH03111073 U JP H03111073U
Authority
JP
Japan
Prior art keywords
image data
frame memory
circuit
memory circuit
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012890U
Other languages
Japanese (ja)
Other versions
JP2539786Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2012890U priority Critical patent/JP2539786Y2/en
Publication of JPH03111073U publication Critical patent/JPH03111073U/ja
Application granted granted Critical
Publication of JP2539786Y2 publication Critical patent/JP2539786Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例による映像信号伝送
装置を示すブロツク図、第2図は動きベクトル検
出回路の動作の説明に供する略線図、第3図は画
像重畳処理部分を示すブロツク図、第4図はデコ
ーダ回路を示すブロツク図、第5図は従来の画像
合成方法を示すブロツク図、第6図はその合成画
像を示す略線図である。 10……映像信号伝送装置、14,52……ビ
デオ信号処理回路、16……動きベクトル検出回
路、18,50……デコーダ回路、60……アナ
ログデイジタル変換回路、63,66,78,8
0,82,90,92……フレームメモリ回路、
94……デイジタルアナログ変換回路。
FIG. 1 is a block diagram showing a video signal transmission device according to an embodiment of the present invention, FIG. 2 is a schematic diagram illustrating the operation of a motion vector detection circuit, and FIG. 3 is a block diagram showing an image superimposition processing section. , FIG. 4 is a block diagram showing a decoder circuit, FIG. 5 is a block diagram showing a conventional image synthesis method, and FIG. 6 is a schematic diagram showing the synthesized image. 10... Video signal transmission device, 14, 52... Video signal processing circuit, 16... Motion vector detection circuit, 18, 50... Decoder circuit, 60... Analog-digital conversion circuit, 63, 66, 78, 8
0, 82, 90, 92... frame memory circuit,
94...Digital-to-analog conversion circuit.

Claims (1)

【実用新案登録請求の範囲】 入力映像信号をデイジタル映像信号に変換する
アナログデイジタル変換回路と、 上記デイジタル映像信号を第1のフレームメモ
リ回路に格納して所定のタイミングで読み出し、
上記デイジタル映像信号を所定フオーマツトの画
像データに変換するフオーマツト変換回路と、 所定の基準画像データに基づいて、上記画像デ
ータの動きベクトルを検出する動きベクトル検出
回路と、 上記動きベクトルに基づいて、上記画像データ
を符号化処理して伝送データを生成する符号化回
路と、 上記伝送データを復号して第2のフレームメモ
リ回路に格納した後、所定のタイミングで読み出
して上記基準画像データを上記動きベクトル検出
回路に出力する送信用デコーダ回路と、 伝送対象から到来する伝送データを復号して受
信画像データを作成する受信用デコーダ回路と、 上記受信画像データを第3のフレームメモリ回
路に格納した後、所定のタイミングで読み出し、
上記受信用画像データを上記デイジタル映像信号
のフオーマツトに変換して受信デイジタル映像信
号を出力するフオーマツト逆変換回路と、 上記受信デイジタル映像信号をアナログ信号に
変換するデイジタルアナログ変換回路と を具え、 上記受信画像データを第3のフレームメモリ回
路に格納する際、所定のタイミングで、上記受信
画像データに代えて、上記第1のフレームメモリ
回路から出力される上記画像データ又は上記第2
のフレームメモリ回路から出力される上記基準画
像データを格納し、 上記受信画像データの画像の一部に、上記第1
のフレームメモリ回路から出力される上記画像デ
ータの画像又は上記第2のフレームメモリ回路か
ら出力される上記基準画像データの画像を表示す
る ことを特徴とする映像信号伝送装置。
[Claims for Utility Model Registration] An analog-to-digital conversion circuit for converting an input video signal into a digital video signal; storing the digital video signal in a first frame memory circuit and reading it out at a predetermined timing;
a format conversion circuit that converts the digital video signal into image data in a predetermined format; a motion vector detection circuit that detects a motion vector of the image data based on predetermined reference image data; an encoding circuit that encodes image data to generate transmission data; and a second frame memory circuit that decodes the transmission data and stores it in a second frame memory circuit, reads it out at a predetermined timing, and converts the reference image data into the motion vector. a transmission decoder circuit that outputs to the detection circuit; a reception decoder circuit that decodes transmission data arriving from the transmission target to create reception image data; and after storing the reception image data in a third frame memory circuit, Read at the specified timing,
a format inverse conversion circuit that converts the received image data into the format of the digital video signal and outputs the received digital video signal; and a digital-to-analog conversion circuit that converts the received digital video signal into an analog signal; When storing image data in the third frame memory circuit, at a predetermined timing, instead of the received image data, the image data output from the first frame memory circuit or the second frame memory circuit is stored.
the reference image data outputted from the frame memory circuit of the first frame memory circuit;
A video signal transmission device characterized in that it displays an image of the image data output from the frame memory circuit or an image of the reference image data output from the second frame memory circuit.
JP2012890U 1990-02-28 1990-02-28 Video signal transmission device Expired - Lifetime JP2539786Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012890U JP2539786Y2 (en) 1990-02-28 1990-02-28 Video signal transmission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012890U JP2539786Y2 (en) 1990-02-28 1990-02-28 Video signal transmission device

Publications (2)

Publication Number Publication Date
JPH03111073U true JPH03111073U (en) 1991-11-14
JP2539786Y2 JP2539786Y2 (en) 1997-06-25

Family

ID=31523226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012890U Expired - Lifetime JP2539786Y2 (en) 1990-02-28 1990-02-28 Video signal transmission device

Country Status (1)

Country Link
JP (1) JP2539786Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113163103A (en) * 2020-01-07 2021-07-23 半导体元件工业有限责任公司 Imaging device with image conversion circuit for improved motion detection

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60178784A (en) * 1984-02-24 1985-09-12 Nukada Fumiaki Video transmitter/receiver

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60178784A (en) * 1984-02-24 1985-09-12 Nukada Fumiaki Video transmitter/receiver

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113163103A (en) * 2020-01-07 2021-07-23 半导体元件工业有限责任公司 Imaging device with image conversion circuit for improved motion detection
US11812168B2 (en) 2020-01-07 2023-11-07 Semiconductor Components Industries, Llc Imaging devices with image transform circuitry for improved motion detection
US12294790B2 (en) 2020-01-07 2025-05-06 Semiconductor Components Industries, Llc Imaging devices with image transform circuitry for improved motion detection

Also Published As

Publication number Publication date
JP2539786Y2 (en) 1997-06-25

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Legal Events

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EXPY Cancellation because of completion of term