JPH0311423A - String data processing mechanism - Google Patents

Abstract

PURPOSE:To continuously process string data by providing two registers to hold the string data, and executing shift merge due to the beginning byte position of data alternately for two operands. CONSTITUTION:First of all, the data beginning byte positions of a first operand and a second operand are set respectively in a byte position registers 2, 3. Next, the data of the first operand is read in from main storage. The read-in data is inputted to a shifter 4 through a bus 8. The shifter 4 executes four kinds of shift functions according to the beginning byte position. The function of 'through' in the case of the byte position of 00, the function of 'left rotate' in the case of 01, the function of 'exchange' in the case of 10, and the function of 'right rotate' in the case of 11 are executed respectively. Next, the data of the second operand is similarly read in, and the merge is executed. After that, the first operand and the second operand are read in alternately, and the data read in the shifter 4 is inputted to the register 5 through the path 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a string data processing mechanism, and particularly to a string data processing mechanism in a processor controlled by firmware instructions.

[Conventional technology]

Traditionally, this type of string processing mechanism has either processed string data one bike at a time, or performed an operation after reading the data of one operand in line with the starting byte position of the data of the other operand. There were two processing methods.

[Problem to be solved by the invention]

Among the conventional string processing methods described above, when string data is processed one byte at a time, the number of memory accesses increases, resulting in poor efficiency and slow execution speed.

In addition, in the method of reading the data of the other operand according to the data start byte position of one operand, processing such as determining the start byte position is complicated, so there is a high possibility that execution speed will decrease and bugs will be introduced. There is a drawback.

[Means to solve the problem]

The string data processing mechanism of the present invention is configured to be able to read and operate on the string data of two operands without being aware of the starting byte position of the data, boundaries, etc. means for holding byte positions for two operands; means for shifting data read from main memory according to contents of a start byte position register; means for holding data output from the shifter in a first merge register; means for holding data output from the main memory in a second merge register; means for re-inputting the output of the first merge register into the second merge register; and data read from the main memory and the output of the second merge register. and means for instructing the hardware using firmware instructions.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 2 is a schematic diagram showing a merge function of the selector 7 shown in the figure.

1 is a data bus, 2 and 3 are registers that store the data start byte position of the operand, 4 is a shifter that shifts data from the main memory according to the contents of registers 2 and 3, 5 and 6
is a register that holds data read from main memory,
7 is a selector that merges data from register 5 and data from main memory according to the contents of registers 2 and 3; 8 and 9;
10.11 is a data bus.

Next, the operation will be explained. FIG. 3 is a schematic diagram showing an example of an operand supplied to the shifter 4 shown in FIG.
The figure is a schematic diagram showing the state transition of the register shown in FIG. 1.

String data is arranged in the main memory without boundary restrictions, while data reading from the main memory is usually performed in units of 4 bytes.

Therefore, we will consider a mechanism that uses hardware to process string data on the main memory in the form of aligned 4 bytes.

The two least significant bits of the start address of the string data are the start byte position of the string data.

Hereinafter, a case will be considered in which the string data of two operands are operated.

First, the data start byte positions of the first and second operands are set in byte position registers 2 and 3, respectively. Next, the data of the first operand is read from the main memory. The read data is input to the shifter 4 via a path 8.

The shifter 4 executes four types of shift functions depending on the starting byte position. If the byte position is 00, the function is through, if it is 01, it is a left rotation, if it is 10, it is an exchange, and if it is 11, it is a right rotation.
Rotate.

In the string data shown in FIG. 3, a left rotation is performed in the lick shifter where the data start byte position is 01, and the data is set in the shifter 4 at timing T1.

Next, read the next data of the first operand and use shifter 4.
The contents of are transferred to register 5.

At this time, the contents of the shifter 4 and the contents of the register 5 are merged by the selector 7. Selector 7 selects the data in each byte of register 5 and shifter 4 according to the contents of the byte position register. If the byte position is 00, all bytes of register 5 are selected, and if the byte position is 01, the upper 3 bytes of register 5 and shifter 4 are selected. The lower 1 byte of 10, the upper 2 bytes of register 5 and the lower 2 bytes of shifter 4, 11, register 5
The upper 1 byte of shifter 4 and the lower 3 bytes of shifter 4 are merged.

Next, the data of the second operand is similarly read and merged at timings T3 and T4. After that, the first operand and the second operand are read alternately, and the shifter 4 is read at timing T s and T 6.
The data read into register 5 via path 10.
is input to.

In this way, the first string data reading timing T1. After T2, T3, and T4, by reading the first operand and the second operand alternately, it becomes possible to continuously calculate string data.

All of the above operations are performed according to firmware instructions,
Timing T1 is the first step of reading the first operand, timing T2 is the middle step of reading the first operand, timing T3 is the first step of reading the second operand, timing T4 is the middle step of reading the second operand, timing T5. T
6 corresponds to the middle stage of the first and second operand reads, respectively.

〔Effect of the invention〕

As explained above, the present invention has two registers that hold string data read from main memory, and performs shift-merging based on the starting byte position of the data alternately for two operands, thereby achieving efficient memory access. Since it is possible to continuously process string data while performing the above operations, it is possible to improve the processing and calculation speed of string data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a schematic diagram showing the merging function of the selector shown in FIG. 1, and FIG.
1 is a schematic diagram showing an example of an operand supplied to the shifter shown in FIG. 1, and FIG. 4 is a schematic diagram showing a state transition of the register shown in FIG. 1. 1...Data bus, 2, 3...Register, 4...
Shifter, 5.6... Register, 7... Selector, 8
~11...Data bus.

Claims (1)

[Claims] In a processor that operates under the control of a firmware instruction, a shifter capable of taking in data from a data bus and shifting and holding the data according to the instruction of the firmware instruction, and storing an output of the shifter according to the instruction of the firmware instruction. a first merge register that can store the output of the shifter or the output of the first merge register according to firmware instructions; two sets of registers into which a starting byte position can be loaded; and a selector for merging the output of the shifter and the output of the second merge register according to a value of the byte position register selected by an instruction of a firmware instruction; input string data of two operands alternately into the shifter, then input the data into a first merge register, and merge the output of the shifter with the output of the second merge register while reading the operands alternately. A string data processing mechanism characterized in that string operations are performed continuously by performing string operations.