JPH03116499A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a desired binary output and to obtain the device of high reliability by controlling a conducting state of a first transistor by an output of an inverter means, and preventing a current from being allowed to flow steadily to a nonvolatile storage element. CONSTITUTION:A flip-flop is constituted by connecting an input and an output, and an output and an input of a CMOS inverter of transistors QP11, QN11, and a CMOS inverter of transistors QP12, QN12, and by an output of the latter CMOS inverter, a gate of the transistor QP11 is controlled. That is, to an output terminal of the flip-flop, a nonvolatile storage element whose impedance is varied nonvolatilely and the capacity are connected, and a ratio of capacities C1, C2 connected to two output terminals, respectively of the flip-flop is varied by varying an impedance state of the nonvolatile storage element under the condition of C1>C2. In such a way, when a power source is turned on, a stable state of the flip-flop can be varied, and accordingly, necessity for allowing a current to flow at all times to the nonvolatile storage element is eliminated, and reliability of the device becomes high.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device suitable for use when switching a regular circuit to a spare circuit.

[Technical Background of the Invention] Recently, in semiconductor integrated circuit devices, especially semiconductor memories, regular memory cell circuits and spare memory cell circuits are formed, and when a defective bit is found in the regular memory cell circuit during manufacturing. Increasingly, memory cells have a redundancy function in which the defective bit portion is replaced with a spare memory cell circuit. This is because even if a normal memory cell circuit has just one defective cell, the memory as a whole is defective, and such a memory is discarded as a defective product.

In other words, as memory capacity increases, the probability of defective memory cells occurring increases, and if defective memory is thrown away, the cost of the product becomes extremely high. Put it away.

Therefore, in order to improve the overall yield, a method has been adopted in which a spare memory cell circuit is formed and used by switching when a part of the regular memory cell circuit is defective.

FIG. 1 is a block diagram of a semiconductor memory in which the spare memory cell circuit described above is formed. In the figure, 1 is an address buffer to which an address signal is applied, and the output from this address buffer 1 is applied to a regular address decoder 2 and a spare address decoder 3 in parallel. The decoded output of the regular address decoder 2 is given to the regular memory cell circuit 4, and one row line in the regular memory cell circuit 4 is selected by this decoded output, and then connected to this selected row line. Data is stored in and read from memory cells. Further, the decoding operation of the regular address decoder 2 is controlled by the output from the spare address decoder 3. The decode output of the spare RDO1/S decoder 3 is given to the spare memory cell circuit 5, a memory cell in the spare memory cell circuit 5 is selected by this decode output, and then data is transferred to the selected memory cell. Data is stored or read; pick.

On the other hand, depending on the configuration of the spare address decoder 3, there may be a defective bit in the regular memory cell circuit 4, and when replacing this defective part with a memory cell in the spare memory cell circuit 5, the memory cell It is also possible to perform control using an exchange control signal output from an exchange control signal generator 6 in which information for exchange is written in advance in a nonvolatile memory element. In other words, in a semiconductor memory having such a configuration, if there is no defective bit in the regular memory cell circuit 4, the exchange control signal is not output, and only the regular address decoder 2 operates to replace the memory in the regular memory cell circuit 4. A cell is accessed. On the other hand, if there is a defective bit in the regular memory circuit 4, the spare address decoder 3 is programmed in advance so as to obtain a decoding output that corrects the row or column address containing the defective bit, and the exchange control signal is The nonvolatile memory element is programmed so that an exchange control signal of "1" level or "0" level can be obtained from the generating section 6. Therefore, address buffer 1 is now used as regular memory cell circuit 4.
When an output corresponding to the row or column address containing the defective bit is obtained, the spare address decoder 3 selects a memory cell in the spare memory cell circuit 5.

Furthermore, the decoding output of the spare address decoder 3 at this time stops the decoding operation of the regular address decoder 2, and the regular memory cell circuit 4 is not accessed. Through such operations, the regular memory cell circuit 4
The defective part inside is replaced with a spare memory cell circuit 5.

FIG. 2(a) $(b) shows the exchange control signal generating section 6
This is a circuit diagram showing the conventional configuration of . The circuit shown in Fig. 2 (,) inserts a phase element F made of polysilicon, etc., which is a type of nonvolatile memory element, between the power supply VD application point and the output terminal Out. Insert an enhancement mode MOS transistor Q8 for programming between the ground point and the output terminal Ou.
MOS in depletion mode between
) Insert Lanzosta QD, MOS Tra/, Zosta Q8
Give programs a and p to day and day, and
The gate of the OS Tra/Zosta QD is connected to the ground point. In addition, the circuit shown in FIG. 2(b) has Q MOS transistors in enhancement mode for programming inserted between the power supply VD application point and the output terminal Out.
Similarly, a depletion mode MOS transistor QD is inserted between the power supply VD application point and the output terminal Out.
In addition, a fuse element F is inserted between the output terminal and the ground point 7, a program signal P is applied to the MOS transistors Q (r-), and the date of the MOS transistor Qn is connected to the output terminal Out. It is.

In the circuit of Fig. 2(a), when the fuse element F is not blown, the level of the output terminal Out is MOS (MOS).
Depending on the resistance ratio between the Lan-Zostar QD and the fuse element F, the ``''1#1# level is determined. On the other hand, when a program signal P of @1'' level is applied to the dart of MOS transistor Q8, this transistor turns on and the fuse element F
A large current flows through the 67-use element F, and the fuse I element F is blown out by the heat generated at this time.
When the transistor Q is fused, the signal P becomes @0# level again.

is cut on, and the output terminal Out is then discharged to the '0' level via the transistor QD.Then, when the signal at the output terminal Out, that is, the level of the exchange control signal is, for example, at the '1' level, the reserve The decoding operation of the address decoder 3 is stopped, and the decoding operation is performed when the address decoder 3 is at the "0" level, for example.

In the circuit of Fig. 2 (with), contrary to the circuit of Fig. 2 (a), when the fuse element F is not blown, the level of the output terminal Out is MOS) The resistance between the transistor QD and the fuse element F When the 11" level Glodarum signal P is applied to the dart of the transistor Qg, the fuse element F is blown out in the same way as above, and then the output terminal Out is kept at the '0" level.
It is charged to the 1" level through D. In this case, when the level of the signal at the output terminal Out, that is, the exchange control signal, is, for example, the "0" level, the decoding operation of the spare address decoder 3 is stopped. For example, the decoding operation is performed when the signal is at the "l" level.

FIG. 3 shows an example of the configuration of one decoding circuit of the spare address decoder 3 when the exchange control signal generating section 6 is not used frequently. This circuit is inserted between a depletion mode transistor QLD for load and a plurality of enhancement mode transistors QDR and transistor QLD for driving each attribution force output from the address buffer 1. Multiple fuse elements FB
It consists of

In such a decoding circuit, among the memory cells of the regular memory cell circuit 4, for example, the fourth address Ao=
Al-...If the one corresponding to An=O is defective, is the code output corresponding to this address?'? )
Each phase element F3 is connected to f log run, AOHAl +...An as a date input) -y in; t x p The I# element FR is blown out. be done. Therefore, A, = A,
=...=A When =0, the spare memory cell at that address is accessed.

[Problems in the Background Art] By the way, in the conventional exchange control signal generator shown in FIGS. 2(a) and 2(b) or the conventional backup decoder shown in FIG. 3, the fuse element F is not blown. When there is no current flowing through it. On the other hand, the width of the pattern shape of the fuse element F is made extremely narrow so that it can be easily blown out. For this reason, it is not preferable in terms of reliability to constantly flow current through the phase element F. For example, if noise is added to the power supply VD for some reason, or if the power supply voltage is erroneously increased, an abnormal current will flow through the fuse element F, and there is a risk that it will be erroneously blown out.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and it is possible to obtain a desired binary output without constantly passing current to a nonvolatile memory element (fuse element), thereby improving reliability. The aim is to provide a semiconductor integrated circuit device with high performance.

[Summary of the Invention] The present invention connects a nonvolatile memory element whose impedance nonvolatilely changes and a capacitor to the output terminal of a flip-flop, and connects each to the output terminals of the two flip-flops. By changing the impedance state of the non-volatile memory element under the condition of C,>Cz, the ratio of capacitance 1cllc2 is changed, thereby making it possible to change the stable state of the flip 70 when a stain source is input. This eliminates the need for constant current to flow through the nonvolatile memory element, thereby increasing the reliability of the device. [Embodiments of the Invention] An embodiment of the present invention will be described below with reference to the drawings. :":invent. Although FIG. 7 is a circuit diagram of the same embodiment, explanation will be given first from FIG. 4. As shown in FIG. 4, enhancement mode MO8) transistor Q6°Q, 21. , FJ Depression MO8) Ran Zosta QD1 *Q
A capacitor C is connected to the output N of the flip-flop FL constituted by D2 via a polysilicon fuse F serving as a nonvolatile memory element.

On the other hand, a capacitor C2 is connected to the other output N of the flip roller 7'FL1.

In Fig. 4, if the capacitance relationship is CI>C2, then the current V
When D is turned on, the output Nl is charged faster than N1, so the potential of the output N1 becomes higher than the potential of Nl, so the transistor QE is turned on, the transistor Q is turned off, and the flip-flop FL is charged as N2. =″′0゜N , :=: 11
Stable at 11 #. At this time, the output is N! becomes the above-mentioned exchange control signal, and since N1=10# at this time, the spare circuit (spare memory cell) is not used, and at this time, the polysilicon fuse F is in a low impedance state. When the preliminary circuit is used, the polysilicon fuse F is blown by, for example, a laser. At this time, pre-silicon fuse F
corresponds to a high impedance state. Therefore, the capacity C!
is disconnected from output N1, and now when the power is turned on, output N
1 rises to a high potential more quickly than Nl, transistor QE2 is turned on and tQg1 is turned off, resulting in output N1=1. N,
="O", the backup circuit is brought into operation by the output N1 which becomes the exchange control signal.

In this way, no current will constantly flow through the polysilicon fuse F. Also, polysilicon fuse F
When is in a low impedance state, the output 8ri is at the 10'' level, so after the power is turned on, current only flows through the polysilicon fuse F for a moment to charge the capacitor c1.

In FIG. 5, high resistance polysilicon R is used in place of the polysilicon fuse F in FIG. Normally, this R has a high resistance, but it becomes low resistance by laser annealing. The resistance is reduced in this way when the backup circuit is used. That is, since the capacitance relationship is C, )C2, when the resistance of polysilicon R is reduced, the output N! is at the "0" level, Nl level, and at this time, Nl becomes the exchange control signal. In this case as well, the same signal as in the case of FIG. 4 can be supplied.

FIG. 6 shows a specific example applied to a preliminary decoder.

Enhancement mode MO8) Transistor Q'g1+
Q'I, 2, depletion mode MO8) The slip 70 tube FL2 constituted by transistors QD1 p QD2 has a capacitor c3 connected to each of its outputs N2 p N 2 via a polysilicon phase F1 pF2. Then, depending on the defective address, one of the polysilicon fuses F1pF2 is cut off. Enhancement mode MO8) transistor Qz3yQi4 is connected to the output N2 and N2 of flip-flora 7'FL2,
A signal N is input to r-) of these transistors. An enhancement mode MO8) transistor QE5 is connected between the supply end of the address signal Ax and the supply end of the signal A'X.
is inserted, and an enhancement mode MoS transistor Qg6 is inserted between the supply end of the address signal line and the supply end of the signal A' line. The gate of the transistors Q and 5 is connected to the output N2 of the flip-flop FL2. 6 f-) is connected to output N2. The spare decoder is enhancement mode MO8) transistor QEX p Qr, x1rQEX2 + ”'
Qt27 p Qga, depression mode MO
3) Consists of transistor QD5, transistor QEX
+ QEX+ t QEX2 y ”' QE7 p
Qga 9- is signal A' + A'X1,
A'X2...'rl p Nl is supplied, and the output end of this spare decoder is connected to a spare memory cell via a buffer Bu.

In FIG. 6, the address signal A z ” ” 0 ”
Assuming that there is a defective memory cell at the address +AX=“1”, the polysilicon phase F2 is cut off. Therefore, in the flip-flop FL2, the capacitance of the output N is larger than N2, so when the power supply VD is turned on, N2=
When ``'0''t Nz = -11, transistor Q5 is turned on.

Q, 6 is turned off, and the address signal Ax is transferred to the transistor Q,
, 5 to A' and to the gate of transistor 8. Similarly, the transistor.

The signals A'X1*"N2t... from other address inputs are input to the Q darts, □, . . . .

These signals are output after the fuse F1tF2(r) is disconnected in accordance with a defective address in a configuration similar to the 7 lip-flop system shown in FIG. When the signals A'X, A'X1 + A'X2 t... all reach the "0" level, the spare memory is selected. - On the other hand, when the spare memory cell is not used, signal N1 = "0" + NI = "'1 #'1 # level transistor QB3F QE4 p Q10 is on, Qg
Since a is turned off and the output signal of the spare memory cell is also at the "0" level, it will not be selected.

FIG. 7 shows an embodiment of the present invention. This configuration includes a CMOS inverter of transistors QP111 QNl 1,
Transistor QP12 + QNl. The feature is that a flip-flop is formed by connecting the input/output with the CMOS inverter, and the dirt control of the transistor QP11 is performed by the output of the latter CMOS inverter.

Assuming that the condition of C+)Cz mentioned above is satisfied,
If the capacitance of C1 is selected to be very large, for example infinite, it is equivalent to the case where 7S-s is directly connected to ground, so C1 is not particularly necessary.

It is clear that no current flows through the fuse in this case as well. Specifically speaking, in FIG. 7, the ground "0" becomes the input to the CMOS inverter means having Qp12+QN1° via the fuse F.

Therefore, the output of this CMOS inverter is "1#", and since this "1" becomes the gate input of the p-type transistor Q, 11, QPll is turned off and no current flows through the fuse F.

In addition, as shown in Fig. 7 (CMOS circuit), this effect is particularly effective. This is because, as shown in the figure, if a flip-flop circuit using p-channel transistors Q11 * Qp 12 ! N-channel transistors Q11 pQ12 is used, non-volatile This is because the current does not constantly flow through the storage element F, and the current flowing through the exchange control signal generation circuit itself shown in FIG. 7 also becomes zero.

[Effects of the Invention] As explained above, according to the present invention, since current does not constantly flow through the nonvolatile memory element, data is not written erroneously due to power supply noise, etc., and power consumption is reduced. It is possible to provide a highly reliable semiconductor integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a semiconductor memory in which a spare memory cell circuit is formed, FIGS. 2 and 3 are partial detailed circuit diagrams of the same configuration, and FIGS. 4 to 6 are detailed explanations of the present invention. 7 are circuit diagrams of an embodiment of the present invention. FL,...Flip-flop circuit, C1tC2...
Capacitance, N1+N1...Output end, F-...Polysilicon fuse, R...High resistance polysilicon, QPll
1 Qp12...P' channel type transistor, QN
lj j QNl2...N-channel transistor.

Claims (1)

[Claims] A nonvolatile memory element, a first transistor (Q_P_1_1) connected between the nonvolatile memory element and a power supply, and a potential at a connection point between the first transistor and the nonvolatile memory element. Inverter means (Q_P_1_2, Q_N_
1_2) and a capacitor (C_2) connected to the output terminal of the inverter means, the conduction state of the first transistor is controlled by the output of the inverter means, and the nonvolatile memory element is provided with a constant state of conduction. A semiconductor integrated circuit device characterized in that no current flows through the semiconductor integrated circuit device.