JPH03116837A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form metal silicide films at prescribed positions on a semiconductor with good selectivity and to contrive the prevention of the generation of an interelectrode or inter-wiring leak by a method wherein a metal film is formed on the semiconductor, oxygen ions are selectively implanted in this metal film and a part, in which the ions are not implanted, of the metal film is silicified. CONSTITUTION:A metal film 8 is formed on a semiconductor, oxygen ions are selectively implanted in this film 8, that is, are limitatively implanted in selected parts of the film 8 and a part only, in which the ions are not implanted, of the film 8 is silicified. By performing in such a way, a diffusion of Si is inhibited in the oxygen ion implanted parts at the time of silicification due to a heat treatment subsequent to the silicification of the part only, in which the ions are not implanted. Thereby, a silicification of the film 8 can be performed with selectivity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device using silicide technology.

[Summary of the invention]

The present invention forms a metal film on a semiconductor, selectively implants oxygen ions into the metal film, and silicides the metal film to which no ions are implanted, thereby forming a metal silicide film at a predetermined position on the semiconductor. can be formed with good selectivity.

[Conventional technology]

A metal silicide film is formed in a self-aligned manner on a predetermined region of a silicon semiconductor, for example, to form an electrode or wiring with low sheet resistance.
f Aligned 5iliside: 5ALI
SIDE) technology is available. Note that a technique for forming a silicide layer is disclosed in, for example, Japanese Unexamined Patent Publication No. 84064/1983.

A method of manufacturing a so-called MOS-LSI including an insulated gate field effect transistor MOS-FET as a circuit element using conventional salicide technology will be described with reference to FIGS. 3A to 3F.

In this case, the end of the drain adjacent to the gate of the MOS-PET is a so-called LDD (Light
lyDoped Drain) structure, first, as shown in Figure 3A, for example, p-type silicon (Si) is used.
On the surface of the semiconductor substrate (1), a thick silicon oxide film insulating layer (hereinafter referred to as field insulating layer) (2) is formed by thermal oxidation selectively in the field area other than the element forming area, and then the field insulating layer is formed. On the surface of the element formation region surrounded by (2), a gate insulating film (3) made of, for example, a SiO□ film is formed by thermal oxidation. ) to form.

Next, as shown in FIG. 3B, using the gate electrode (4), gate insulating film (3), and field insulating layer (2) as masks, a layer of, for example, arsenic (As) is applied to the semiconductor substrate (1) f. A low concentration source region (5,) and a low concentration drain region (61) are formed by ion-implanting n-type impurities at a low concentration.

Thereafter, for example, CVD (chemical vapor deposition method: Chem
After forming a 5i02 film on the entire surface using the ical vapor deposition method, this S
The iO2 film is etched in a direction perpendicular to the surface of the substrate (1) to form a sidewall (7) of 5i02 on the sidewall of the gate electrode (4) as shown in FIG. 3C.

Next, as shown in the third diagram, using the gate electrode (4), sidewall (field insulating layer) and field insulating layer (2) as masks, an n-type impurity such as phosphorus (P) is added to the semiconductor substrate (1). High concentration source region (5□
) and a highly doped drain region (6□) are formed. Thereafter, heat treatment is performed to activate the implanted impurities. As a result, the source region (5) consisting of regions (5,) and (5□) and the drain region (6) consisting of regions (61) and (6□) are self-contained with respect to the gate electrode (4). Consistently formed. These gate electrode (4), source region (5), and drain region (6) constitute an LDD type n-channel MO3-FET.

As shown in FIG. 3E, a metal film (8) such as a titanium (Ti) film is formed on the entire surface by sputtering or the like, and then heat treatment is performed at a low temperature of about 600°C in an argon (Ar) atmosphere. conduct. As a result, the metal film (8), that is, Ti
Semiconductor (Si) in the source region (5) and drain region (6) where the film and this Ti film (8) are in direct contact.
By this reaction, the metal film (8) on the source region (5) and drain region (6) is silicided, and the silicide film (titanium silinide in this example) (
9a) and (9b) are formed.

After this, as shown in FIG. 3F, the unreacted metal film (8)
is removed by wet etching or the like to form a source electrode and a drain electrode in ohmic contact with the source region (5) and drain region (6) made of the silicide films (9a) and (9b).

However, in the MOS-LSI manufacturing method using such conventional salicide technology, in the reaction process of forming the silicide film explained in FIG. 3E, the circle shown schematically in FIG.
As silicon (Si) atoms move (diffuse) into the metal film (8) as shown by the marks and arrows, the Si atoms move (diffuse) into the titanium (
Ti) diffuses into the metal film (8). For this reason, for example, a silicide film is formed extending over the field insulating layer (2) and remains without being removed even when the metal film (8) is etched. If a wiring section is formed, there are problems such as leaks or short circuits occurring between the wiring section and the wiring section.

[Problems to be Solved by the Invention] The present invention aims to provide a method for manufacturing a semiconductor device that can form a low-resistance metal silicide film with good selectivity on a predetermined portion of a semiconductor.

[Means for Solving the Problem] As shown in FIG. 1E, the present invention provides a metal film (
8) is formed, and oxygen ions are selectively implanted into the metal film (8), that is, in a limited manner in selected portions, and only the metal film (8) to which ions are not implanted is silicided.

[Function] As described above, in the present invention, oxygen ions are selectively implanted into the metal film (8), and by doing so, oxygen ions are implanted during subsequent silicidation by heat treatment. This suppresses the diffusion of Si in the areas where the metal film (8) has been silicided, thereby selectively silicidating the metal film (8).

FIG. 2 shows the Si region already shown on the St substrate shown as region a.
In a model in which an O□ layer and a Ti layer shown in region C are laminated, when O゛ is implanted into the Ti layer, Si and Si after annealing at 800''C in a N2 atmosphere are measured by Auger electron spectroscopy. , 0, and Ti. According to this, it can be seen that the presence of oxygen O in region C suppresses the movement of Si into the Ti layer.

In the method of the present invention, silicide is prevented from creeping up onto SiO□ due to the effect of suppressing the movement of Si due to zero oxygen.

〔Example〕

Hereinafter, one embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG.

In this embodiment, the LD
MOS-LSI that uses D-type MOS-FET as a circuit element
In this case, as shown in FIG. 1A, first, for example, a P-type silicon (Si) semiconductor substrate (1
), a thick silicon oxide film insulation layer (field insulation layer (2)) is selectively formed by thermal oxidation in the field area other than the element formation area, and the element formation surrounded by the field insulation layer (2) is formed. A gate insulating film (3) made of, for example, a 5iOz film by thermal oxidation or the like is formed on the surface of the region, and a gate electrode (4) made of, for example, tungsten silicide (WSiz) is formed thereon.

Next, as shown in FIG. 1B, using the gate electrode (4), the gate insulating film (3), and the field insulating layer (2) as masks, apply a film of e.g. A low concentration source region (51) and a low concentration drain region (61) are formed by ion-implanting n-type impurities such as the following at a low concentration.

Thereafter, a SiO□ film is formed on the entire surface by, for example, a CVD method, and then, as shown in FIG. 1C, this SiO□ film is etched onto a substrate ( 1) to form a side wall (7) made of Sin on the side wall of the gate electrode (4).

Next, as shown in the first diagram, a gate electrode (4) is formed.

Using the sidewalls (7) and the field insulating layer (2) as masks, n-type impurities such as arsenic (As) are ion-implanted into the semiconductor substrate (1) at a high concentration to form a high-concentration source region (5). and a high concentration drain region (62) is formed. Thereafter, heat treatment is performed to activate the implanted impurities. As a result, the source region (5) consisting of regions (51) and (5□) and the drain region (6) consisting of regions (6υ and (6□)) are self-aligned with respect to the gate electrode (4). The gate electrode (4), source region (5), and drain region (6) constitute an LDD type n-channel MO3-FET.

As shown in FIG. 1E, a metal film (8) such as a titanium (Ti) film is deposited on the entire surface by sputtering or the like to a thickness of 400 mm.

Next, as shown in Figure 1F, photoresist is applied,
By pattern exposure and development processing, an oxygen ion implantation mask (lO) is formed in a pattern that covers the area other than the area in which extended silicide should be avoided, in this example, the field insulating layer (2). Then, oxygen ions O° are implanted into the Ti metal film (8) in the portions not covered by the ion implantation mask (10).

Next, as a first heat treatment, for example, PTA (Rap
idThermal Annealing). As a result, the metal film (8), that is, the Ti film, and this Ti film (
8) reacts with the semiconductor (Sυ) in the source region (5) and drain region (6) that are in direct contact with each other, and this reaction causes the source region (5) and drain region (6) to react as shown in FIG. 1G. The upper metal film (8) is a silicide film, in this example titanium silicide (9a).
, (9b) are formed.

The titanium silicide film in this case is mainly Ti5Si.
2 and TiSi.

As illustrated in FIG.
remove.

Next, a second heat treatment is performed at 800°C to 100″C.
For example, PTA such as lamp annealing is performed at a high temperature of about 800'C to form silicide films (9a) and (9b).
That is, in this example, the titanium silicide film is mainly T.
Let it be iSi2. In this way, the silicide film (9a)
and (9b), forming a source electrode and a drain electrode in ohmic contact with the source region (5) and drain region (6).

Note that in the above example, the gate electrode (4) is formed of, for example, tungsten silicide;
In this case, it is necessary to ensure that no diffusion occurs from the gate electrode (4) side to the sidewall (force), and that the extension from the silicide films (9a) and (9b) due to the diffusion of Si from the source and drain sides is This is a case where the gate electrode (4) and the silicide Dff (9a) as the source and drain electrodes do not reach the electrode (4).
and (9b), if there is a risk of leakage or short circuit between the ion implantation mask (1
By eliminating the pattern 0) also on the sidewall (7) and implanting oxygen ions into it, the silicide films (9a) and (9b)
It is also possible to limit the extension of the gate electrode (4) toward the gate electrode (4).

Further, in the above example, the case where the semiconductor substrate (1) is a Si semiconductor substrate was explained, but the present invention can be applied when a silicide film is formed on a Si semiconductor formed on an insulating substrate or an insulating layer. I can do it.

Further, the present invention provides “double n-channel type MOS-L
It can be applied to manufacturing various semiconductor devices such as not only SI but also P-Z' channel type MO3-LSI, CMO5-LSI, and bipolar LSI other than MOS-LSI.

〔Effect of the invention〕

According to the method for manufacturing a semiconductor device according to the present invention, the creeping formation of silicide on the insulating film during silicidation annealing is suppressed by oxygen ion implantation, so that a metal silicide film is selectively formed on the semiconductor. It can be easily formed, and therefore, it is possible to avoid leaks between electrodes or wiring, deterioration of characteristics such as short circuits, and occurrence of defective products.

[Brief explanation of drawings]

Figures 1A-H are cross-sectional views of each process showing one embodiment of the method for manufacturing a semiconductor device according to the present invention, and Figure 2 is a stacked model of Si, 0, and T determined by Auger electron spectroscopy.
3A-F are line cross-sectional views at each step of the conventional method, and FIG. 4 is a spectrum diagram for Si on a metal film.
It is a schematic diagram showing a diffusion mode. (1) is a semiconductor substrate, (2) is a field insulating layer, (3
) is a gate insulating film, (4) is a gate electrode, (5) is a source region, (6) is a drain region, (7) is a side wall, (8) is a metal film, (9a) and (9b) are silicide The membrane, (lO) is the ion implantation mask. Agent Hidemori Matsukuma! 3 diagrams showing the 4th IM side view of the conventional Ida + 1

Claims (1)

[Claims] Manufacture of a semiconductor device characterized by forming a metal film on a semiconductor, selectively implanting oxygen ions into the metal film, and siliciding the metal film to which no ions have been implanted. Method.