JPH03116865A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To lessen the occurrence of refresh failures by a method wherein the distances between a substrate potential generating circuit and memory cell sections are elongated respectively by a factor correspondent to an indirect peripheral circuit and a direct peripheral circuit or to a bonding pad and a direct peripheral circuit. CONSTITUTION:When a substrate voltage generating circuit 9 is arranged in a region between an indirect peripheral circuit 8 and bonding pads 3, the circuit 9 is arranged at the center of a part between the upper and the lower memory cell arrays 10. At the same time, the indirect peripheral circuit 8 and a direct peripheral circuit 7 are arranged on a region between the circuit 9 and the upper memory cell arrays 10, and the source and the drain diffusion layers of MISFETs absorb minor carriers induced in the circuit 9. The bonding pads 3 and the direct peripheral circuit 7 are arranged on a region between the circuit 7 and the lower memory cell arrays 10, and the source and the drain diffusion layers of the MISFETs arranged adjacent to them absorb minor carriers induced in the circuit 9. By this setup, a semiconductor memory device of this design can be improved in electrical reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a technique that is effective when applied to a semiconductor memory device equipped with a substrate voltage generation circuit.

[Conventional technology]

In a semiconductor memory device having a DRAM with a storage capacity of 1M or 4M [bit], a plurality of external terminals (ponding pads) are arranged at the upper and lower ends of the semiconductor substrate, and the memory is placed in the area between the bonding pads. Cell array section, direct peripheral circuit, indirect peripheral circuit.

Each of the substrate voltage generation circuits is arranged.

The memory cell array portion is disposed in the center between the upper and lower bonding pads of the semiconductor substrate, and occupies most of the surface area of the semiconductor substrate. This memory cell array section is divided into a total of four sections, for example, two on the upper side and two on the lower side, to increase information access speed. In each divided memory cell array section, l[bjt
A plurality of memory cells storing l information are arranged in rows and columns.

This memory cell includes a memory cell selection MO3FET,
It consists of an information storage capacitive element (capacitor) connected in series with this MO3FET for memory cell selection.

Between the two memory cell array sections on the divided side and between the two memory cell array sections on the lower side, respectively.

A Y decoder circuit is arranged to open complementary data lines. Furthermore, an X decoder circuit and a word driver circuit for driving word lines are arranged between the upper memory cell array section and the lower memory cell array section. These Y decoder circuits, X decoder circuits, etc. constitute direct peripheral circuits that directly drive the memory cell array section.

A RAS circuit is located between the upper memory cell array section and the bonding pad placed at the upper end.

Clock system circuits such as CAS system circuits are arranged. Address related circuits such as an X address buffer circuit and a Y address buffer circuit are arranged between the lower memory cell array section and the lower end bonding pad. These clock-related circuits and address-related circuits constitute an indirect peripheral circuit that controls the direct peripheral circuit.

Of the indirect peripheral circuits, a substrate voltage generation circuit is arranged in a region between the lower indirect peripheral circuit where the address system circuit is arranged and the lower end bonding pad. This substrate voltage generation circuit operates to lower the semiconductor substrate to a voltage lower than the ground potential of the circuit, for example by -2, for the purpose of reducing the parasitic capacitance added to the source and drain regions of the MOSFET.
,5 to -3.5 [V]. This substrate voltage generation circuit generates minority carriers through its operation.

These minority carriers invade the capacitor that constitutes the memory cell and change the amount of charge as information stored in this capacitor, and a refresh operation is performed based on this changed amount of charge, thereby preventing refresh failure. provoke. Therefore, as described above, this substrate voltage generation circuit is placed near the bonding pad on the lower end side, and an indirect peripheral circuit is placed between this substrate voltage generation circuit and the memory cell array section, and By increasing the separation distance, the MOS constituting the indirect peripheral circuit
This increases the probability that minority carriers can be absorbed by diffusion layers such as the source and train of the FET, thereby reducing the occurrence of the above-mentioned refresh failure.

On the other hand, storage capacity continues to increase, reaching 16 M [bit]
A semiconductor memory device having a DRAM with a storage capacity of This semiconductor memory device is mounted in a resin-sealed package, but the increase in the size of the semiconductor substrate is large compared to the increase in the size of the resin-sealed package. It becomes difficult to pull the leash around. Therefore, this semiconductor memory device has +LOC
It is mounted in a resin-sealed package with a (Lead OnChip) structure.

When the semiconductor memory device is mounted in a resin-sealed package with this LOC structure, the leads are routed on the surface of the semiconductor memory device, so the bonding pads are used for IM or 4M [bit] semiconductor memory device. Unlike the layout of , it is placed in the center of the semiconductor substrate. The memory cell array section is divided vertically or horizontally around this bonding pad. A direct peripheral circuit includes a region between the bonding pad and the memory cell array section.
They are arranged along each of the memory cell array sections.

- of the bonding pad and the direct peripheral circuit.
In the region between the two sides, the substrate voltage generation circuit and the indirect peripheral circuit are arranged in order from the direct peripheral circuit side.

Regarding this type of DRAM, for example,
It is described in No. 161859.

[Problem to be solved by the invention]

However, as a result of studying the above-mentioned prior art, the inventor found the following problems.

The aforementioned DRAM with a capacity of 16 M [bit]
In this case, each of the direct peripheral circuit, indirect peripheral circuit, bonding pad, and substrate voltage generation circuit is arranged for the reasons described below.

The direct peripheral circuit is arranged along the memory cell array section in order to shorten the wiring length between the direct peripheral circuit and the memory cell array section and increase the operating speed of the semiconductor memory device. .

The bonding pads are arranged in a plurality of columns, for example, two columns, based on the increase in the number of address signals as the capacity increases.

These two rows of pounding pads.

1ilrl during wire bonding! In order to prevent damage or destruction to the indirect peripheral circuits and direct peripheral circuits, the circuits are placed sufficiently separated from the indirect peripheral circuits and direct peripheral circuits, and in order to minimize this separation area, the circuits are placed in one place. centrally located.

Further, the indirect peripheral circuit includes an indirect peripheral circuit that controls a direct peripheral circuit arranged along an upper memory cell array section, and an indirect peripheral circuit that controls a direct peripheral circuit arranged along a lower memory cell array section. It is divided into circuit and
In order to improve the degree of integration, these are constructed in one piece. Further, this indirect peripheral circuit is placed in the center between the upper and lower direct peripheral circuits in order to equalize the wiring lengths between the upper and lower direct peripheral circuits and to increase the operating speed. In other words, an increase in the operating speed of the DRAM can be achieved by sequentially arranging the direct peripheral circuits and the memory cell array section above and below at uniform distances, centering on the single indirect peripheral circuit.

For the above reasons, the respective locations of the direct peripheral circuit, the bonding pad, and the indirect peripheral circuit are determined. As a result, the substrate voltage generation circuit is arranged in the area between the indirect peripheral circuit and one of the direct peripheral circuits (the area between the indirect peripheral circuit and the other direct peripheral circuit), as described above. ). Therefore, only one of the direct peripheral circuits is disposed in the region between the substrate voltage generation circuit and the upper memory cell array section, and since it is not possible to provide sufficient separation between the two, the substrate voltage The minority carriers generated by the generation circuit cannot be absorbed completely by this direct peripheral circuit. As a result,
When unabsorbed minority carriers enter the memory cell array and change the amount of charge as information stored in the capacitors that make up the memory cell, a refresh operation is performed based on this changed amount of charge.

There was a problem that refresh failures occurred frequently.

An object of the present invention is to provide a technique that can improve electrical reliability in a semiconductor memory device equipped with a substrate voltage generation circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In a semiconductor memory device equipped with a substrate voltage generation circuit, 2
Direct peripheral circuits are arranged along the respective memory cell array sections in the region between the two memory cell array sections, and indirect peripheral circuits are arranged along the one direct peripheral circuit in the region between the respective direct peripheral circuits. An external terminal is arranged along the other direct peripheral circuit, and the substrate voltage generation circuit is arranged in a region between the indirect peripheral circuit and the external terminal.

[For production]

According to the above-described means, the distance between the substrate voltage generation circuit and each memory cell array section is set by one distance corresponding to an indirect peripheral circuit and a direct peripheral circuit, or a distance corresponding to a bonding pad and a direct peripheral circuit. Therefore, it is possible to reduce the intrusion of minority carriers generated in the substrate voltage generation circuit into the memory cell array portion, and to reduce the occurrence of refresh failures due to the minority carriers. Thereby, the electrical reliability of the semiconductor memory device can be improved.

[Embodiments of the invention]

An embodiment of the present invention will be specifically described below with reference to the drawings.

In all the figures for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

First, a schematic configuration of a mounted state of a semiconductor memory device having a DRAM, which is an embodiment of the present invention, will be explained using FIG. 2 (plan view). A semiconductor memory device having this DRAM is mounted in a resin-sealed package with an LOC structure.

As shown in FIG. 2, the semiconductor memory device of the embodiment is composed of a semiconductor substrate 1. As shown in FIG. This semiconductor substrate 1 is made of, for example, single crystal silicon.

As described above, this semiconductor substrate 1 is mounted in a resin-sealed package of LOC structure 6, that is, the semiconductor substrate 1 is sealed by the resin-sealed portion 2.

On the surface of the central portion of the semiconductor substrate 1, a plurality of bonding pads (external terminals) 3 are arranged in two rows in the left-right direction, although the layout is not limited to this.

Inner leads 5 routed on the semiconductor substrate 1 are connected to each of the bonding pads 3 with bonding wires 4 interposed therebetween.

An outer lead 6 is integrally connected to the inner lead 5.

In this manner, the semiconductor substrate 1 is mounted on the resin-sealed package with the LOC structure, and the inner leads 5 are routed on the surface of the semiconductor substrate 1.

It is possible to reduce the size of the resin-sealed portion 2 and downsize the resin-sealed package.

In the same Figure 2, the area surrounded by the -dotted chain line includes a direct peripheral circuit (7), an indirect peripheral circuit (8), and a substrate voltage generation circuit (9).
are arranged.

Next, the arrangement of each circuit in the semiconductor substrate 1 is shown in FIG.
This will be explained using a circuit block diagram).

As shown in FIG. 1, on the surface of the semiconductor substrate 1,
Memory cell array section 10, direct peripheral circuit 7, ■! ,rI
jI connection peripheral circuit 8. A bonding pad 3 and a substrate voltage generation circuit 9 are respectively arranged.

The memory cell array section 10 is divided into four parts, each of which is arranged vertically and horizontally, although it is not limited thereto. This memory cell array part! 0, a plurality of memory cells are arranged in rows and columns, although not shown. This memory cell is composed of a series circuit of a memory cell selection MISFET and an information storage capacitive element (capacitor) connected in series with the memory cell selection MISFET. Charge as information is stored in this capacitor.

The direct peripheral circuit 11 arranged between the left and right divided memory cell array sections 10 is mainly composed of a Y decoder circuit. Between the memory cell array sections 10 divided into the upper and lower sections, the upper and lower memory cell array sections 10
The direct peripheral circuit 7 arranged along the line is mainly composed of a word driver circuit and an X decoder circuit.

In the region between the direct peripheral circuits 7, the nD peripheral circuit 8 is arranged along one of the upper direct peripheral circuits 7. The indirect peripheral circuit 8 is mainly composed of, for example, an address buffer circuit, a clock system circuit, and a redundant circuit.

In the area between the direct peripheral circuits 7, a plurality of bonding pads 3 are provided along the other direct peripheral circuit 7 on the lower side.
are arranged in two rows in the left and right direction.

A substrate voltage generation circuit 9 is arranged in a region between the indirect peripheral circuit 8 and the bonding pad 9. When this substrate voltage generation circuit 9 is placed between the bonding pads 3 arranged in the two rows, the arrangement of the bonding pads 3 bypasses this substrate voltage generation circuit 9, resulting in a concave shape. , As a result, the direct peripheral circuit 7,
Each of the indirect peripheral circuits 8 also becomes concave. If each of the direct peripheral circuits 71 and indirect peripheral circuits 8 has a concave shape, the power supply wiring and signal wiring connected to each element constituting each of the direct peripheral circuits 71 and indirect peripheral circuits 8 should be shaped into the concave shape described above. You need to bend it accordingly. In order to bend the power supply wiring and signal wiring, it is necessary to provide an additional area for bending the power supply wiring and signal wiring, which reduces the degree of integration.

Therefore, the substrate voltage generation circuit 9 is not arranged between the bonding pads 3 arranged in two rows, and the substrate voltage generation circuit 9 is placed in a region different from the region where the bonding pads 3 are arranged.
The substrate voltage generating circuit 9 is arranged. This substrate voltage generation circuit 9 operates to maintain the semiconductor substrate 1 at an external ground potential of 1, for example -2,5 to -3,5 lower than O [V].
Set the potential to [V]. This substrate voltage generation circuit 9 has a third
As shown in the figure (equivalent circuit diagram), mainly capacitor C□
MISFETQ connected to oscillator 12 via
It consists of Q2. In this substrate voltage generation circuit 9, minority carriers are generated when the clock pulse inputted from the oscillator 12 fluctuates. These minority carriers are injected into the semiconductor substrate 1 via the MISFET Q2. When the minority carriers injected into the semiconductor substrate 1 enter the memory cell array section 10, the amount of charge as information stored in the capacitors constituting the memory cell array changes, so a refresh operation is performed based on the changed amount of charge. If this is done, a refresh failure will occur.

Here, as described above, the substrate voltage generation circuit 9 is arranged in the area between the indirect peripheral circuit 8 and the bonding pad 3. As a result, the substrate voltage generating circuit 9 is placed in the center between the upper and lower memory cell array sections 10 of the semiconductor substrate 1. Therefore, the distance between the substrate voltage generation circuit 9 and the memory cell array section 10 can be equalized and maximized.

At the same time, the indirect peripheral circuit 8. Each of the direct peripheral circuits 7 is arranged, and the diffusion layers of the sources, drains, etc. of MISFETs constituting these circuits can absorb the minority carriers generated in the substrate voltage generating circuit 9. Further, in the region between the substrate voltage generation circuit 9 and the lower memory cell array section 10, the bonding pad 3. Each of the direct peripheral circuits 7 is arranged, and an MIS constituting an electrostatic protection circuit arranged near the direct peripheral circuit 7 and the bonding pad 3
Expanded rF1 layers such as source and drain of FET.

Minority carriers generated by the substrate voltage generating circuit 9 can be absorbed. Therefore, the distance between the substrate voltage generation circuit 9 and the memory cell array section 10 is equalized and increased, and the indirect peripheral circuit 8 is provided between the two.
and the direct peripheral circuit 7 or the bonding pad 3
and the direct peripheral circuit 7 are arranged, and minority carriers can be absorbed by the diffusion layers of these circuits.
Intrusion of minority carriers into the memory cell array portion 1G is reduced, and occurrence of refresh failures due to minority carriers can be reduced. Due to this.

Electrical reliability of a semiconductor memory device can be improved.

The present inventor believes that if the distance between the substrate voltage generation circuit 9 and the memory cell array section 10 is approximately 600 [μm], and there is a diffusion layer such as the source and drain region of the MISFET between the two, the above-mentioned According to this embodiment, which has been confirmed to be able to absorb minority carriers and sufficiently reduce the occurrence of refresh defects, the distance between the substrate voltage generation circuit 9 and the memory cell array section 1G is approximately 1000 μm. It can be taken to some extent.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.

For example, in this embodiment, the bonding pad 3 is
Although an example in which the pads 3 are arranged in rows has been shown, the present invention can also arrange the pads 3 on two sides or in a plurality of rows.

Further, although an example has been shown in which the pounding pads 3 are arranged in the left-right direction, the present invention has a structure in which the pounding pads 3
can also be arranged vertically. In this case, each of the direct peripheral circuit 7 and the indirect peripheral circuit 8 is arranged along the arrangement of the bonding pads 3.

Further, in the present invention, the positions of the bonding pad 3 and the indirect peripheral circuit 8 can be interchanged.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

Electrical reliability can be improved in a semiconductor memory device including a substrate voltage generation circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a semiconductor memory device having a DRAM which is an embodiment of the present invention. FIG. 2 is a plan view schematically showing the overall configuration of a resin-sealed package with an LOC structure on which the semiconductor memory device is mounted, and FIG. 3 is an equivalent circuit diagram of a substrate voltage generation circuit. In the figure, 1... semiconductor substrate, 3... bonding pad, 7,! ! ...Direct peripheral circuit, 8...Indirect peripheral circuit. 9...Substrate voltage generation circuit, 10...Memory cell array section.

Claims (1)

[Claims] 1. Each of at least two memory cell array sections, a direct peripheral circuit that controls each memory cell array section, an indirect peripheral circuit that controls the direct peripheral circuit, an external terminal, and a substrate voltage generation circuit. In the semiconductor memory device, the direct peripheral circuit is arranged along the respective memory cell array parts in a region between the two memory cell array parts, and one direct peripheral circuit is arranged in the region between the respective direct peripheral circuits. The indirect peripheral circuit is arranged along the other direct peripheral circuit, and the external terminal is arranged along the other direct peripheral circuit, and the substrate voltage generation circuit is arranged in a region between the indirect peripheral circuit and the external terminal. A semiconductor storage device. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a DRAM. 3. The semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is mounted in a resin-sealed package having an LOC structure.