JPH031231A - Microprogram controller - Google Patents

Abstract

PURPOSE:To shorten the effective time of a microinstruction by attaching one or more conditional branch satisfying/unsatisfying signals on every micro branching condition bank. CONSTITUTION:The subject controller is equipped with a second selector 214 which receives the branching condition satisfying/unsatisfying signal outputted from each of plural first selectors 213-0 to 213-7 and selects and outputs one of the signals by replying to selection information. As far as a micro branching instruction to be executed is an instruction in which a signal COND 00, COND 01, or COND 02 are set as the branch satisfying/unsatisfying signal, the condi tional branch satisfying/unsatisfying(MTAKENE) signal 110 goes to the signal COND 00, COND 01, or COND 02 though the selector 214 designates any bank based on the content of a register BASEL 215. Thereby, it is not required to perform the execution of a bank switching microinstruction, and especially, since a branching instruction referring to the signals COND-00-02 is used fre quently, the number of steps of the microprogram can be remarkably reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to microprograms, and particularly to a control method for conditional branch instructions of a microprogram in a microprocessor (hereinafter referred to as a microprogram control device) controlled by a microprogram. .

[Conventional technology]

In a microprogram controller, each instruction stored in a program memory and programmable by a user is read out as a microinstruction and processed by executing a corresponding series of microinstructions. , a series of microinstructions corresponding to each microinstruction is stored in a microinstruction memory. A microinstruction has address information in the microinstruction memory, and when a microinstruction to be executed is supplied, that address information specifies the start address of a series of corresponding microinstructions. Generally, a microinstruction has a conditional branch. Instructions (hereinafter referred to as micro branch instructions) are prepared, and branch conditions of the micro branch instructions (hereinafter referred to as micro branch conditions) are generated by decoding the values and states of each internal resource of the micro program control device.

In order to implement microinstructions using microinstructions, it is necessary to refer to the values and states of specific internal resources of the microprogram control device according to the function of each microinstruction. Therefore, the types of microbranch conditions are required to realize all the microinstructions supplied by the microphrogram control device, and the same number of types of microbranch instructions as the microbranch conditions are required. However, the word length of the microinstructions stored in the microinstruction memory is finite, and it is not possible to have more types of microinstruction branch instructions than can be identified by the word length.

The word length of a microinstruction is determined by hardware limitations of the microprogram controller, and therefore it is not possible to ensure a sufficient word length to identify the required microbranch instruction. Moreover, since a one-word micro-branch instruction has not only branch condition information but also opcode and branch destination address information, only a portion of the word length of the micro-branch instruction is actually allocated to identifying the branch condition information ( Hereinafter, the portion assigned to identify the branch condition information of the micro branch instruction will be referred to as the micro branch instruction identification field).

Therefore, in order to realize more types of micro branch instructions than the number of micro branch instructions that can be identified by the micro branch instruction identification field, multiple sets of a large number of micro branch conditions are set, with a predetermined number of micro branch conditions as one set. (Hereinafter, one set of micro branch conditions divided in this way will be referred to as a micro branch condition bank). Furthermore, a bank selection register whose contents are set by a dedicated micro instruction is provided, and the contents of the register are There is a method in which one of the micro branch condition banks is specified according to the bank selection register, and one of the micro branch conditions held by the micro branch condition bank specified by this bank selection register is selected based on the contents of the micro branch instruction identification field. It is taken.

[Problem to be solved by the invention]

In recent years, microprocessors using the microprogram control system are required to execute not only basic instructions such as arithmetic and logic operation instructions and transfer instructions, but also advanced instructions such as privileged instructions and transfer instructions rather than characters. It is necessary to write a micro-program with a complex algorithm that requires several micro-branch conditions. Since the only branch condition that can be identified by the contents of one micro-branch instruction identification field is one micro-branch condition that one micro-branch condition bank has, requiring a large number of micro-conditional branches means that frequent micro-branch conditions This means that banks must be switched. To switch micro branch condition banks, a microinstruction must be executed to set a value in the bank selection register. That is, the number of microinstructions for switching micro conditional branch banks also increases, and the number of steps in the microprogram increases. An increase in the number of microprogram steps reduces the processing speed of the microinstructions realized by the microinstructions, resulting in deterioration in the performance of the microprogram control device.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a microprogram control device that improves the processing speed of microinstructions.

Another object of the present invention is to provide a microprogram control device that can handle a large number of microconditional branches without increasing the number of microprogram steps.

[Means to solve the problem]

The microprogram control device according to the present invention includes a plurality of first branch conditions, each of which receives a plurality of branch condition satisfaction/failure signals.
a plurality of first selectors that select and output one branch condition satisfied/unfulfilled signal in response to the contents of a predetermined field in a micro branch instruction; one selector among these first selectors; A register that stores selection information for selecting the - time, and a register that receives branch condition fulfillment/unfulfillment signals output from each of the plurality of first selectors, selects one of them in response to the selection information, and outputs it. and a second selector that commonly supplies one or more branch condition satisfied/unsatisfied signals to each of the plurality of first selectors, and executes the branch condition satisfied/unsatisfied signal output from the second selector. It is characterized in that it is taken/untaken information of a conditional branch instructed by a micro-branch instruction.

In this way, one or more conditional branch taken/untaken signals are commonly supplied to each first selector, so by using this signal as branch condition information for frequently used micro branch instructions, Therefore, there is no need to switch conditional branch banks, and the number of microprogram steps can be reduced.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The starting address of a series of microprograms to implement the microinstruction read from the program memory (not shown) is in register (STADQ) 1.
00 and held until the execution of that microprogram ends. The start address stored in the register 100 is the start address of the microinstruction (BEGINE).
) signal 112 causes multiplexer (MPX) 10
1 to the register (MAR) lO2. 104 is a multiplexer (MPX), which receives a branch condition fulfillment/unfulfillment signal (MT
When the branch is not taken, the MAR 102 is selected, and when the branch is taken, the output from the head address generator (TARGET) 109 is selected.

The output of MPX 104 is stored in register (MA) 105, updated by 1 by incrementer 103, and supplied to MPXIOI.

During execution of a series of microprograms for one microinstruction, the MPXIOI selects the output of the incrementer 103. Therefore, the contents of MA 105 are updated one by one unless a branch condition is satisfied during the execution of a series of microprograms. The contents of the MA 105 are supplied as address information to the microinstruction memory 106 storing the microprogram, and the microinstruction at the address specified by the address is read out from the memo 47106.
It is transferred to the microinstruction register (MI) 107. M
The microinstruction stored in I 107 is sent to decoder 10.
If the instruction is a micro branch instruction, the branch destination address information contained therein is decoded by TA.
Supplied to RGETI O9. TABGETl 09
generates a branch destination address by referring to this information as well as the store address information of the MAR 102, and supplies it to the MPX 104.

Defood information from the decoder 108 is supplied to the instruction execution unit 110 via the bus 1081, and predetermined arithmetic processing is executed. On the other hand, conditional branch information from decoder 108 is supplied to branch control unit 111 via bus 1082. This unit) 111 receives information indicating the values and states of each internal resource of the execution unit 110 via the bus 1101, and responds to information from the bus 1082 to determine whether a conditional branch is established or not.
A failure signal (MTAKENE) 1110 is generated.

Thus, microinstruction memo! The microprogram written in J106 is executed.

Referring to FIG. 2, the branch control unit 111 includes a branch condition establishment/unestablishment decoder 211, eight first selectors 2,
13-0 to 213-7, one second selector 214,
Two registers (BRCH3EL, BASEL) 2
12.215, and AND gate 216. The decoder 211 decodes information indicating the values and states of internal resources supplied from the execution unit 110 via the bus 1101, and generates a large number of branch condition fulfillment/unfulfillment signals C0NDOO to C0ND42. For example, C0NDOO is an arithmetic logic unit (ALU) of the execution unit 110 (not shown).
) is related to the computation result zero detection signal that is generated every time a computation is performed, and when the signal is zero, it becomes an active level (that is, a conditional branch is established), and when it is not zero, it becomes an inactive level (branch does not take place). Therefore, the micro branch instruction that causes a branch when the zero detection signal is zero refers to the signal C0NDOO. Similarly, C0NDOI
CONDO2 is referred to as a branch condition satisfied/unsatisfied signal related to the carry detection signal and sign detection signal generated each time the ALU performs an operation. Other signal C0ND
O3 to C0ND42 are also referred to as branch condition fulfillment/unfulfillment signals respectively related to other status signals of the ALU and the values and status of other internal resources. In this way, the decoder 211 generates a large number of branch condition establishment/unestablishment signals.

On the other hand, in a micro branch instruction, as described above, the number of bits in the micro branch instruction identification field is small, and therefore it is not possible to specify all the branch condition fulfillment/unfulfillment signals C0NDOO to C0ND42 using only the information in the field.

In this embodiment, the identification field has a length of 4 bits. Therefore, the number of signals that can be specified in the same field is 16. This identification field information is loaded into register (BRCH8EL) 212 via bus 1082 from decoder 108 and further via bus 1111. The contents of the BRCH3EL 212 are commonly supplied to eight first selectors 213-0 to 213-7. Therefore, each of the first selectors 213-0 to 213-7 has 16 input terminals SIO to 5I15, and the BR
One of them is selected in accordance with the data from CH8EL212 and outputted from output node SO. Each selector 21
3 receives eight branch condition establishment/non-establishment signals C0ND from the decoder 211, but according to the present invention, three branch condition establishment/unestablishment signals C0NDOO, C0NDO1, C0
NDO2 is commonly supplied to each of the first selectors 213-0 to 213-7. As mentioned above, the signal C0N
DOO, C0NDO1, C0ND O2 are each AL
It is referred to as a conditional branch taken/not taken signal related to U's zero, carry, and sign signals, which are frequently used as micro-branch conditions. As a result, B.R.C.
When the information specifying the signal C0NDOO is stored in the H8EL 212, all the first selectors 213-0 to 213-0
3-7 selects and outputs the signal C0NDOO. Similarly, information to RRCH8EL212 is sent to signal C0N.
D01. When specifying C0NDO2, all selectors 213-0 to 213-7 output the same signal. The conditional branch establishment/unestablishment signal output from each selector 13-0 to 213-7 is sent to the second selector 21.
4. The second selector 214 is BASEL21
In response to the bank selection information stored in 5, one of the eight input signals is selected and output.

BASEL215 has a bank selection (switching) microinstruction memo! By being read from J106 and executed,
3-bit selection information is stored.

The output of the selector 214 is taken out as the specified conditional branch establishment/unestablishment signal MTAKEN and is sent to the AND gate 21.
6. The other input of gate 216 is provided via bus 1082 with a signal 1112 indicating a micro branch instruction. therefore,
If the instruction read from the memory 106 is a micro branch instruction and the branch condition of the instruction is satisfied, the signal MTAK
ENE1110 becomes active level and MPXIO
! ! MA1 is the branch destination address from TRAGET109.
Transfer to 05.

According to this configuration, as long as the micro branch instruction to be executed is an instruction that uses the signal C0NDOO, C0NDO1, or C0NDO2 as the branch taken/untaken signal, the selector 2
No matter which bank is designated by 14 according to the contents of BASEL 215, the MTAKENE signal 1110 becomes the signal C0NDO0°01 or 02. Therefore, execution of the bank switching microinstruction becomes unnecessary. In particular, signal C
Since branch instructions that refer to 0NDO0, 01, and 02 are frequently used as described above, the reduction in the number of microprogram steps is significant. In addition, the signal C0ND
As a result of commonly inputting O0, 01, and 02 to all first selectors 213, the number of selectors 213 may increase compared to when those signals are supplied to only one selector, but the designation of the selector , that is, bank switching is
BASEL215. Since it can be controlled by the second selector 214, the bit length of the identification field of the micro branch instruction does not increase at all.

FIG. 3 shows a branch control unit 1 according to another embodiment of the present invention.
11, and the difference from Fig. 2 is BASE
A signal BEGIN is supplied to L215 to initialize it. That is, BASEL 215 is initialized at the start of execution of a series of microinstruction routines for each microinstruction, and specifies the bank of selector 213-0.

Therefore, as the conditional branch taken/untaken signals C0NDO3 to C0ND15 to be supplied to the first selector 213-0, the signals that are most frequently referenced next to the signals C0ND00 to C0ND O2 are used, or the microinstructions are divided into categories and are often used. By using a conditional branch take/fail signal for a micro branch instruction for executing a micro instruction of the category to be obtained, the number of steps in the microphrogram can be further reduced.

〔Effect of the invention〕

As described above, according to the present invention, since each micro-branch condition bank has one or more conditional branch take/fail signals in common, the number of micro-instruction steps for realizing the micro-instruction can be reduced. can reduce the execution time of microinstructions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram of the branch control unit shown in FIG. 1, and FIG. 3 is a block diagram of a branch control unit according to another embodiment of the present invention. It is. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A plurality of first selectors, each of which receives a plurality of branch condition taken/untaken signals, and which select and output one conditional branch taken/untaken signal in response to the contents of a predetermined field in a micro branch instruction. 1 selector, a register that temporarily stores selection information for selecting one of the first selectors, and one branch condition in response to the selection information from the signal output from each of the plurality of first selectors. a second selector that selects and outputs whether the branch condition is true or not, one or more branch condition satisfaction/failure signals are commonly input to each of the plurality of first selectors, and the signal is output from the second selector. A microprogram control device characterized in that: is taken as information on whether or not a conditional branch instruction specified by a micro branch instruction is established.