JPH03123328U - - Google Patents
Info
- Publication number
- JPH03123328U JPH03123328U JP3100890U JP3100890U JPH03123328U JP H03123328 U JPH03123328 U JP H03123328U JP 3100890 U JP3100890 U JP 3100890U JP 3100890 U JP3100890 U JP 3100890U JP H03123328 U JPH03123328 U JP H03123328U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- analog
- switches
- closed
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Electronic Switches (AREA)
Description
第１図は、本考案の一実施例にかかるアナログ
信号入力回路の回路ブロツク図、第２図は、第１
図に示される回路で転送される信号のタイミング
チヤート、第３図は、本考案の背景技術にかかる
アナログ信号入力回路ブロツク図、第４図は、第
３図に示される回路で転送される信号のタイミン
グチヤートである。
１……ＣＰＵ、２……オペアンプ、４……カウ
ンタ、５……制御回路、２０……増幅回路、３０
Ａ，３０Ｂ，３１Ａ，３１Ｂ，３２Ａ，３２Ｂ，
３３Ａ，３３Ｂ……アナログスイツチ。
FIG. 1 is a circuit block diagram of an analog signal input circuit according to an embodiment of the present invention, and FIG.
3 is a timing chart of signals transferred by the circuit shown in the figure, FIG. 3 is a block diagram of an analog signal input circuit according to the background art of the present invention, and FIG. 4 is a timing chart of signals transferred by the circuit shown in FIG. 3. This is the timing chart. 1... CPU, 2... operational amplifier, 4... counter, 5... control circuit, 20... amplifier circuit, 30
A, 30B, 31A, 31B, 32A, 32B,
33A, 33B...Analog switch.
Claims (1)
込まれたアナログ信号を増幅して所定の回路に供
給するためのアナログ信号入力回路において、 アナログ信号を取り込むための複数の入力端子
と、 該複数の入力端子の各々に対応して設けられア
ナログ信号を取り込むべき入力端子を切換えるた
めの複数のスイツチと、 該複数のスイツチのそれぞれが閉となることに
より取り込まれたアナログ信号を増幅する１つの
増幅回路と、 前記複数のスイツチのそれぞれについて当該ス
イツチの閉または開を定めるための信号であつて
、前記複数のスイツチのそれぞれに対応する信号
の間で前記閉を定める信号の間には所定時間の前
記開を定める信号が配された信号を発生する制御
信号発生手段と を具えたことを特徴とするアナログ信号入力回路
。[Claim for Utility Model Registration] In an analog signal input circuit for sequentially capturing a plurality of analog signals, amplifying the captured analog signals, and supplying the amplified analog signals to a predetermined circuit, a plurality of input terminals for capturing the analog signals. a plurality of switches provided corresponding to each of the plurality of input terminals for switching the input terminal to which the analog signal is to be taken; and amplifying the analog signal taken in when each of the plurality of switches is closed. one amplifier circuit for determining whether the switch is closed or open for each of the plurality of switches, the signal for determining whether the switch is closed or not between the signals corresponding to each of the plurality of switches; An analog signal input circuit comprising control signal generating means for generating a signal including a signal determining the opening for a predetermined time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3100890U JPH03123328U (en) | 1990-03-28 | 1990-03-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3100890U JPH03123328U (en) | 1990-03-28 | 1990-03-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03123328U true JPH03123328U (en) | 1991-12-16 |
Family
ID=31533735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3100890U Pending JPH03123328U (en) | 1990-03-28 | 1990-03-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03123328U (en) |
-
1990
- 1990-03-28 JP JP3100890U patent/JPH03123328U/ja active Pending