JPH0312464U - - Google Patents
Info
- Publication number
- JPH0312464U JPH0312464U JP7273889U JP7273889U JPH0312464U JP H0312464 U JPH0312464 U JP H0312464U JP 7273889 U JP7273889 U JP 7273889U JP 7273889 U JP7273889 U JP 7273889U JP H0312464 U JPH0312464 U JP H0312464U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- multilayer printed
- printed wiring
- pattern
- characteristic impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002847 impedance measurement Methods 0.000 description 1
Description
第１図はこの考案の一実施例を示す平面図、第
２図は従来多層プリント配線板の平面図、第３図
は多層プリント配線板の一例を示す断面図である
。
１……多層プリント配線板、２……信号パター
ン配線エリア、３……信号パターン非配線エリア
、４……信号パターン、５……特性インピーダン
ス測定パターンである。なお、図中、同一符号は
同一または相当部分を示す。
FIG. 1 is a plan view showing an embodiment of this invention, FIG. 2 is a plan view of a conventional multilayer printed wiring board, and FIG. 3 is a sectional view showing an example of the multilayer printed wiring board. 1... Multilayer printed wiring board, 2... Signal pattern wiring area, 3... Signal pattern non-wiring area, 4... Signal pattern, 5... Characteristic impedance measurement pattern. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
を有したことを特徴とする多層プリント配線板。 A multilayer printed wiring board characterized in that each signal layer has a pattern for measuring characteristic impedance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7273889U JPH0312464U (en) | 1989-06-21 | 1989-06-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7273889U JPH0312464U (en) | 1989-06-21 | 1989-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0312464U true JPH0312464U (en) | 1991-02-07 |
Family
ID=31610941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7273889U Pending JPH0312464U (en) | 1989-06-21 | 1989-06-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0312464U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002067638A1 (en) * | 2001-02-19 | 2002-08-29 | Sony Corporation | Printed wiring board, multilayer printed wiring board, and, method of detecting foreign matter and voids in inner layer of multilayer printed wiring board |
| JP2014093340A (en) * | 2012-11-01 | 2014-05-19 | Nec Corp | Test coupon for managing characteristic impedance and print circuit board with the same |
-
1989
- 1989-06-21 JP JP7273889U patent/JPH0312464U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002067638A1 (en) * | 2001-02-19 | 2002-08-29 | Sony Corporation | Printed wiring board, multilayer printed wiring board, and, method of detecting foreign matter and voids in inner layer of multilayer printed wiring board |
| JP2014093340A (en) * | 2012-11-01 | 2014-05-19 | Nec Corp | Test coupon for managing characteristic impedance and print circuit board with the same |