JPH0312536U - - Google Patents
Info
- Publication number
- JPH0312536U JPH0312536U JP7198389U JP7198389U JPH0312536U JP H0312536 U JPH0312536 U JP H0312536U JP 7198389 U JP7198389 U JP 7198389U JP 7198389 U JP7198389 U JP 7198389U JP H0312536 U JPH0312536 U JP H0312536U
- Authority
- JP
- Japan
- Prior art keywords
- main board
- sub
- receiving device
- broadcast receiving
- satellite broadcast
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000284 extract Substances 0.000 claims 1
- 230000005236 sound signal Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Receiver Circuits (AREA)
- Structure Of Receivers (AREA)
Description
第１図は本考案の一実施例の基板の説明図、第
２図は音声回路部分のブロツク図である。
１…主基板、２…第１副基板、３…第２副基板
、４，６…雌コネクタ、５，７…雄コネクタ、８
，９…端子板。
FIG. 1 is an explanatory diagram of a board according to an embodiment of the present invention, and FIG. 2 is a block diagram of the audio circuit portion. 1... Main board, 2... First sub board, 3... Second sub board, 4, 6... Female connector, 5, 7... Male connector, 8
, 9...Terminal board.
Claims (1)
タ回路、抽出された音声副搬送波を復調する４相
ＤＰＳＫ復調回路、該復調回路からのＰＣＭ信号
をデコードする音声ＰＣＭデコーダ、ＰＣＭデコ
ードされた音声信号を取り込むクロツク再生・デ
ータミユートコントロール回路、及び該コントロ
ール回路からの出力を受ける２系統のデジタルフ
イルタ回路を有する主基板と、Ｄ／Ａコンバータ
及びローパスフイルタを有し且つ上記主基板のデ
ジタルフイルタ回路の一方叉は双方に対してコネ
クタ接続される１個叉は同一構成の２個の副基板
とからなることを特徴とする衛星放送受信装置。 (2) 上記副基板が、上記主基板に対して垂直方
向にコネクタ接続されることを特徴とする実用新
案登録請求の範囲第１項記載の衛星放送受信装置
。 (3) 上記主基板から上記各デジタルフイルタ回
路を除去して、上記２個の副基板に設けたことを
特徴とする実用新案登録請求の範囲第１項記載の
衛星放送受信装置。[Claims for Utility Model Registration] (1) A bandpass filter circuit that extracts audio subcarriers, a 4-phase DPSK demodulation circuit that demodulates the extracted audio subcarriers, and an audio PCM decoder that decodes the PCM signal from the demodulation circuit. , a main board having a clock reproduction/data mute control circuit that takes in a PCM decoded audio signal, and two digital filter circuits that receive output from the control circuit, a D/A converter, and a low-pass filter; A satellite broadcast receiving device comprising one or two sub-boards having the same configuration and connected by a connector to one or both of the digital filter circuits of the main board. (2) The satellite broadcast receiving device according to claim 1, wherein the sub-board is vertically connected to the main board by a connector. (3) The satellite broadcast receiving device according to claim 1, wherein the digital filter circuits are removed from the main board and provided on the two sub-boards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7198389U JPH0312536U (en) | 1989-06-20 | 1989-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7198389U JPH0312536U (en) | 1989-06-20 | 1989-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0312536U true JPH0312536U (en) | 1991-02-07 |
Family
ID=31609508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7198389U Pending JPH0312536U (en) | 1989-06-20 | 1989-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0312536U (en) |
-
1989
- 1989-06-20 JP JP7198389U patent/JPH0312536U/ja active Pending
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