JPH03127157A - Load balance control system for storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a load balance control technology for storage devices.
In particular, the present invention relates to a technique that is effective in controlling the load balance of input/output processing in a storage device shared by a plurality of higher-level processing devices.

[Conventional technology]

For example, external storage devices used in information processing systems, etc. may be equivalent to magnetic disk devices, such as magnetic tape devices, magnetic disk devices, or even semiconductor memory, depending on their operating characteristics, purpose of use, and field of use. Semiconductor disk devices and the like are widely used, which have improved functions and faster response operations.

Furthermore, in response to the increase in the amount of information that systems must process, the storage capacity of such storage devices continues to increase, and system configurations in which a single storage device is shared by multiple central processing units are becoming commonplace. There is.

By the way, when a storage device is shared by multiple central processing units, it is essential to perform exclusive control of access to the storage device between systems. This is performed by a control device interposed between the computer and the storage device.

For example, JP-A-61-62155 and JP-A-61
As with the technology disclosed in Publication No. 86857, when multiple central processing units share a storage device via multiple access routes and a control device intervening in the access route, the usage status of the access route is monitored. A shared memory is provided for storage, and each control device refers to this shared memory, thereby achieving exclusive control by giving priority to responses to access requests from a plurality of higher-level central processing units.

Further, in the technology disclosed in Japanese Patent Application Laid-Open No. 63-146147, etc., a storage device is provided with a memory that stores access status for each access route connected to the storage device,
By appropriately referring to the contents of this memory, the higher-level central processing unit is able to grasp the actual input/output load situation in the storage device.

[Problem to be solved by the invention]

However, although the above-mentioned conventional technology is effective in optimally controlling the access route between the central processing unit and the control unit, it is difficult to control the specific access route between the control unit and the storage device under its control. There is a problem in that it is not possible to prevent the occurrence of input/output load bias.

In other words, in the conventional technology described above, when multiple control devices access a shared access area that is logically arranged in a storage device and there is a conflict of access, the storage device out-bids the conflict on a first-come, first-served basis. It accepts access from the control device and starts input/output processing.

This shared access area is divided into multiple exclusive units in which access from other access routes is inhibited during access from a specific access route, and a series of exclusive units from the control device (access route) currently being accessed. A control method is used in which the control device (access path) remains occupied until the processing (data reading/writing such as updating and deletion) is completed. Therefore, during this time, the shared access area is invisible to other control devices. If the controller is in use, other controllers enter a wait state until the process is completed.

When the series of processing is completed, the storage device simultaneously notifies all the standby control devices to release the occupied state, and with this as an opportunity, the standby control devices control the central processing unit as described above. The access request specified by the response order is issued to the storage device again, but if a conflict as described above occurs between multiple control devices, the winning control device (access route) occupies the shared access area of the storage device and starts input/output processing.

If such operations, such as occupying and releasing the shared access area of the storage device, are performed repeatedly during system operation, the control of the access path between the control unit and the central processing unit is not related to the storage device. In order to temporarily repeat first-come-first-served control, a certain control device (
There is a problem in that the availability and performance of the storage device is impaired because the service is biased, such as accepting only access requests from the access route (access route), and access requests from other access routes are forced to wait for an abnormally long time. .

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a load balance control method for a storage device that can improve the availability of the storage device by controlling the load of human output on the storage device in a well-balanced manner.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the load balance control method for a storage device according to the present invention is a storage device that is connected to a higher-level processing device via a plurality of access paths and a plurality of control devices, and stores data exchanged with the higher-level processing device. A storage device comprising a medium and a transfer circuit that transfers data between the storage medium and a control device, the storage device having a common access area logically arranged within the storage medium and shared by higher-level processing devices. a first means for storing at least one of an access order, an access execution frequency, and an access wait frequency in access via the access route; and an access order, an access execution frequency, and an access wait frequency stored in the first means. and a second means for determining the execution priority of the access requests from each of the plurality of access routes by referring to at least one of the access routes, thereby optimizing the execution order of the access requests from each of the plurality of access routes. This is how it was done.

[Effect]

According to the above-described load balance control method for a storage device of the present invention, the second means provided in the storage device to which a plurality of access paths are connected allows By setting the execution priority of access requests so that the execution priority of access requests from access routes is higher, the execution frequency of access requests is biased towards a specific access route,
This prevents an access request issued from a specific access path from having to wait for an abnormally long time, and improves the availability of the storage device from the perspective of the entire upper central processing unit via a plurality of access paths.

〔Example〕

Hereinafter, an example of a load balance control method for a storage device, which is an embodiment of the present invention, will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of essential parts of a storage device according to an embodiment, and FIG. 2 is a block diagram showing an example of the configuration of a subsystem including this storage device.

First, an overview of the configuration of the subsystem of this embodiment will be explained with reference to FIG.

The semiconductor memory device 1 has a plurality of access paths A.

The access route B, the access route C, the access route D1, and the control device 2°, the control device 3. Control device 3. Control device 5
via a plurality of upper-level central processing units (CP
U) and shared by these central processing units.

The semiconductor storage device 1 includes a relatively large-capacity semiconductor memory 6 as a storage medium, and the storage area of the semiconductor memory 6 consists of a plurality of volumes 0 to n, which are exclusive units, and each volume is: It is logically divided by a software interface in a higher-level control device.

Further, the semiconductor memory device l has a plurality of access paths A,
A plurality of interface circuits 20 .corresponding to each of B, C, and D. Interface circuit 30, interface circuit 40. An interface circuit 50 is provided. Each interface circuit includes a receiver 20a and a driver 20b.

It is composed of a receiver 30a, a driver 30b, a receiver 40a, a driver 40b, a receiver 50a, and a driver 50b, and data, commands, etc. are exchanged between the upper controllers 2 to 5 and the semiconductor memory 6 via the access paths. controls the exchange of information.

Note that the semiconductor memory device l includes a control processor that manages the semiconductor memory 6, and a non-volatile memory device that saves information stored in the volatile semiconductor memory 6 in order to prevent the information from being lost in the event of a power outage. Although it includes a control circuit for controlling the saving/recovery of information between the nonvolatile storage medium and the semiconductor memory 6 and the nonvolatile storage medium, illustrations and explanations thereof will be omitted.

In this case, in the semiconductor memory device 1, between the plurality of interface circuits 20 to 50 and the semiconductor memory 6,
A circuit group 7 having a configuration as described later is provided.

That is, this circuit group 7, as shown in FIG.
It is composed of a selection circuit 70, a priority route determination circuit 71, a control processor 72, a clock circuit 73, and a log information storage section 74.

The log information storage unit 74 stores an in-use flag management table 75.
．． Exclusive release wait flag management table 76゜Access order management queue 77, access reception count counter table 7
8. It consists of an access count counter table 79.

The selection circuit 70 selects the
Access request signals are received on a first-come, first-served basis, and at the timing obtained from the clock circuit 73, information such as the target volume included in the access request signal and which access route the access request signal comes from is determined. Based on this, the contents of the log information storage section 74 are updated, and the priority route determination circuit 7
1, the access request signal is transferred to the access request signal.

The priority route determination circuit 71 determines the priority order of the access routes A-D in a manner described below based on the contents of the log information storage unit 74 updated by the selection circuit 70, and notifies the selection circuit 70 of the determined result. Perform the action. The selection circuit 70 is
Based on the result determined by the priority route determination circuit 71, a signal is issued that gives exclusive rights to the target volume to any of the access routes A-D, and this signal is transmitted to the drivers 20b to 50b of the interface circuit 20.
The information is transmitted to the upper central processing unit (CPU) via the CPU.

Such a selection circuit 70 and priority route determination circuit 71
A series of operations are generally controlled by a control processor 72.

FIGS. 3(a) to 3(e) show, in logical format, an example of the structure of each of the tables that constitute the log information storage section 74.

That is, the in-use flag management table 75 shown in FIG. It is a table that connects any one volume to any access route A.
-D is in use, a flag is set in the corresponding entry.

Upon receiving the access request signal, the selection circuit 70 refers to the in-use flag management table 75, searches for an entry corresponding to the volume targeted by the access route that issued the access request signal, and selects an entry other than the access route. If the flag is set in the entry, it is known that the volume is occupied by another access route, and if the flag is not set in all entries, the access currently being accepted A flag is set in the entry corresponding to the access route that issued the request signal to inhibit access from other access routes.

In addition, the exclusive release wait flag management table 76 is shown in the same figure (
As shown in (b), the selection circuit 70 includes a plurality of entries associating a plurality of access routes A-D with each of the polygon numbers Qn of a plurality of volumes, and the selection circuit 70 selects the in-use flag management table. If it is found that the target volume is already occupied by another access route when referring to 75, a flag is set in the entry specified by the access route and the target volume number, and the entry is placed in an exclusive release waiting state. Display something.

At the time of release of exclusive use, the flag is referenced and the access route is notified that the target volume has been released.

The access order management queue 77 shown in FIG.
Entries corresponding to the number of access routes A-D for each of the volume numbers 0 to n of the plurality of polygons form a queue structure, and the selection circuit 70 selects the interface circuits 20 to 50 (access routes A to 50). D) in order of arrival of access request signals received from the upper side via
Access route A-D is registered in order 4 from .

In other words, access routes A-D registered in order 1
is currently occupying the volume, and other p access routes A to D registered in orders 2 to 4 are in a waiting state in that order.

Therefore, a flag is set in the entry in the in-use flag management table 75 corresponding to the access route registered in order 1, and a flag is set in the entry in the exclusive release waiting flag management table 76 corresponding to the access route registered in order 2 to 4. This means that the flag is set for the corresponding entry.

In the case of this embodiment, as will be described later, the priority route determination circuit 71 appropriately changes the registration status of the access routes in orders 2 to 4 based on a predetermined algorithm or the like.

The access reception count counter table 78 shown in FIG. , the number of times an access request signal is issued to a certain volume from a certain access route is recorded and managed.

In addition, the access waiting number counter table 79 shown in FIG.
Among the number of attempts to access each volume recorded in the access reception number counter table 78, the number of times a waiting state has occurred is recorded and managed.

The priority route determination circuit 71 always refers to the access reception frequency counter table 78 and the access waiting frequency counter table 79, calculates the value (ratio) of the access waiting frequency/access reception frequency, and calculates the value (ratio) of the access waiting frequency/access receiving frequency for each access route A to D. Remember. Then, in the access order management key 5-77,
By appropriately changing the order of access routes A-D that are registered in orders 2 to 4 and in the access waiting state, the value (ratio) of the number of access wait times/number of access receptions for multiple access routes A-D can be averaged. Make sure that it becomes .

That is, the priority route determination circuit 71 changes the access order management key 77 so that the execution order of the access route A to D, which has a larger value and a higher incidence of access waiting, is given a higher execution order.

Since each entry in the access order management key 5-77 has a queue structure, it is deleted when the access route registered in order 1 completes access to the volume.
Entries in orders 2 to 4 are carried forward in order. The priority route determination circuit 71 determines the notification priority of the release of exclusive use to the higher-ranking devices according to the order after the promotion, and the selection circuit 70 notifies the higher-ranking devices of the determined result via the drivers 20b to 50b.

After this notification operation, the access route that issued the access request to the volume is registered at the end (order 4) of the queue corresponding to the policy.

Furthermore, since each entry in the access reception count counter table 78 and the access wait count counter table 79 is a counter, overflow may occur for each volume, but in that case, the access reception count counter table 78 is first read. will overflow.

Therefore, upon detection of an overflow in the access reception frequency counter table 78, the priority route determination circuit 71 makes entries for all access routes A-D corresponding to the volume in the access reception frequency counter table 78 and the access waiting frequency counter table 79. is reset to the initial value of zero, and the number of access wait times for all access routes A-D of the volume stored as described above/
Rewrite based on the value of the number of accesses received (occurrence rate of waiting for access).

For example, if the above-mentioned ratio of a certain access route is 1/10, 10 is written in the entry of the access reception count counter table 78 corresponding to the access route, and the corresponding entry of the access wait count counter table 79 is written. By writing l, the information regarding the degree of access waiting for the access route, etc. is made to match the state immediately before the overflow.

In addition, when restarting the system due to a failure, etc., the in-use flag management table 75 of the log information storage unit 74
~All entries in the access waiting number counter table 79) The IJ is initialized, and if a failure occurs in a specific volume, the entry related to the polynym is initialized.

Hereinafter, an example of the operation of the load balance control method for the storage device of this embodiment will be described with reference to the flowchart shown in FIG. 4 and the like.

In addition, in FIG. 4, processing when a failure occurs is omitted.

First, when an arbitrary central processing unit issues an access request signal to a certain volume in the semiconductor memory 6 of the semiconductor storage device 1, one of the interface circuits 20 to 50 receives the access request signal and sends it to the selection circuit 70. Communicate (step 100).

The selection circuit 70 receives an instruction from the control processor 72 to determine whether the polyname is occupied by another access route, and refers to the in-use flag management table 75 in the log information storage section 74 (step 101). .

The control processor 72 stores the in-use flag management table 75.
If a flag indicating that the volume is in use is not set in any access route, a flag is set in the corresponding entry of the access route to declare occupancy (step 102).

Furthermore, the access route is registered in the order l of the target volume in the access order management queue 77, and at this point, the occupation of the target volume by the access route is confirmed (step 103).

Then, the value of the entry corresponding to the access route of the target volume in the access reception frequency counter table 78 is updated (step 104), the target volume is occupied, and processing such as data writing/reading is started (step 104). 105).

Note that access requests for other volumes from other access routes that occur while the target volume is being accessed by the access route for which occupancy has been confirmed will be accepted.
Processing is performed in parallel.

When the process of step 105 described above is completed (step 1
06), the selection circuit 70 should refer to the exclusive release wait flag management table 76 of the log information storage section 74107)
, check the waiting states of other access routes to the volume (step 108).

At this time, if there is no access waiting for the access route, the flag corresponding to the access route in the in-use flag management table 75 is reset (step 113), and the process ends.

On the other hand, if it is found in step 108 that there is another access route waiting for access to the volume, the entries in orders 2 to 4 corresponding to the volume in the access order management queue 77 are referred to (step 108). 109〉.

At this time, as described above, the orders 2 to 4 are set so that the frequency of access to the volume by each access route is equalized by the replacement operation by the priority route determination circuit 71.

After this reference operation of the access order management key 5-77, the selection circuit 70 resets the flag of the access route of the volume in the in-use flag management table 75 according to the instruction from the control processor 72 (step 11O).

Then, the priority access route is sequentially transmitted to the selection circuit 70 by the priority route determination circuit 71, and the selection circuit 70
In order of priority, a notification that the volume has been released is transmitted to each access route (to the upper side) via each interface circuit 20 to 50 (step 111).
.

After this operation, the selection circuit 70 resets all the lags (of the notified access route) on the exclusive release wait flag management table 76 based on the command from the control processor 72 (step 112).

This completes the process when the specific volume is successfully occupied by an access request from the upper level via the specific access route.

On the other hand, in step 101, if the target volume is occupied by another access route,
The selection circuit 70 sets a flag in the corresponding entry in the exclusive release wait flag management table 76 of the log information storage unit 74 according to the instruction from the control processor 72 (step 114).
.

Then, the access route is registered in one of the entries in order 2 to 4 corresponding to the target volume in the access order management queue 77 (step 115).

Next, in step 116, the value of the entry corresponding to the access route of the target volume in each of the access reception count counter table 78 and the access wait count counter table 79 is added by 1. Step 11
7) After that, the selection circuit 70 informs the interface circuit 2 that the volume requested for access is already being used by another access route to the upper side.
0 to 50 (step 118).

Thereafter, in response to an instruction from the control processor 72, the priority route determination circuit 71 stores the number of accesses received in the counter table 78.
With reference to the access wait count counter table 79 (step 119), the value of access wait count/access reception count (occurrence rate of access wait) is determined and compared with the values of other access routes regarding the volume (step 120).

Then, if the incidence of access waiting for the target volume is lower than that for other access routes, the process remains as is and waits for release of occupancy, and ends the process.

On the other hand, in step 120, if the incidence of access waiting for the target volume is higher for the access route than for other access routes, the priority route determination circuit 71 operates the access order management key 77; The orders 2 to 4 regarding the volume are changed according to the determination result (step 121).

In this way, the access route that has had a low probability of successfully accessing the volume in the past is prioritized (
When the target volume is no longer occupied by another access route, the access wait state is reached until the target volume is released, and when the volume is no longer occupied by another access route, the process is executed with priority.

As described above, in the case of this embodiment, the in-use flag management table 75 of the log information storage section 74 provided in the semiconductor storage device 1. Exclusive release wait flag management table 76, access order management key, -77° access reception count counter table 78. A selection circuit 70 which is provided with an access waiting number counter table 79 and accepts and accepts access requests from the upper side via a plurality of access routes. Priority route determination circuit 7
1, etc., by appropriately referring to the log information storage unit 74, the semiconductor storage device 1 can independently accept and execute access requests generated from a plurality of access routes A to D, for example, by referring to the log information storage unit 74. It becomes possible to appropriately allocate the data so that the frequency of access to a specific volume in a specific semiconductor memory 6 is not biased.

Thereby, the input/output load on the semiconductor storage device 1 can be controlled in a well-balanced manner, and the availability of the semiconductor storage device 1 from the viewpoint of all higher-level central processing units can be improved.

- As a result, there is a concern that, for example, due to biased access to a specific volume from a specific access route, accesses to that volume from other access routes may have to wait an abnormally long time, causing problems such as processing halts. This problem is solved, and the performance and reliability of the external storage subsystem including the semiconductor storage device 1 can be improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the explanation of the above embodiment, a case was described in which the ratio between the number of access requests and the number of access wait occurrences is used as a method for determining the priority of access permission for a specific volume of multiple access routes. However, the present invention is not limited to this, and for example, by performing special initial settings for high-priority access routes during system operation, the priority can be secured and the overall input/output balance of multiple access routes can be controlled. You can.

In addition to simply determining the ratio between the number of access requests and the number of access waits, we can also perform differential/integral processing on the number of access requests and the number of waits to obtain information such as slope/area images. , priorities may be set based on this information.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

That is, the load balance control method for a storage device according to the present invention is a storage device that is connected to a higher-level processing device via a plurality of access paths and a plurality of control devices, and stores data exchanged with the higher-level processing device. A storage device comprising a medium and a transfer circuit that transfers data between the storage medium and the control device, the storage device being logically arranged within the storage medium and shared by the higher-level processing device. a first means for storing at least one of an access order, an access execution frequency, and an access waiting frequency in accessing an access area via the access route; and the access order and access execution stored in the first means. a second means for determining the execution priority of the access request from each of the plurality of access routes by referring to at least one of frequency and access waiting frequency; Since the execution order of access requests is optimized, for example, a second means provided in a storage device to which multiple access routes are connected is used to select an access route that has a larger value of access execution frequency/access waiting frequency. By setting the execution priority of access requests so that the execution priority of access requests is higher, the execution frequency of access requests is biased toward a specific access route, or access requests issued from a specific access route Abnormally long waiting times are reliably avoided, and the availability of the storage device from the perspective of a higher-level central processing unit is improved via multiple access paths.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of main parts of a storage device according to an embodiment. FIG. 2 is a block diagram showing an example of the configuration of a subsystem including the storage device. e) is an explanatory diagram showing an example of the internal configuration of the log information storage unit; FIG. 4 is a flowchart showing an example of the operation of the load balance control method for the storage device of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor storage device, 2, 3, 4.5... Control device, 6... Semiconductor memory, 7... Circuit group, 20-5
0...Interface circuit, 20a to 50a...
Receiver, 20b to 50b... Driver, 70...
Selection circuit, 71...Priority route determination circuit, 72...
Control processor, 73... Clock circuit, 74... Log information storage unit, 75... In-use flag management table, 7
6...Flag management table, 77...Access order management queue 78...Access reception number counter table, 79...Access waiting number counter table,
100-121...Steps showing an example of a storage device load balance control method, A, B, C, D... Access routes.

Claims (1)

[Claims] 1. A storage medium connected to a higher-level processing device via a plurality of access paths and a plurality of control devices and storing data exchanged with the higher-level processing device; a storage device comprising a transfer circuit that transfers data to and from the control device, the access path to a common access area that is logically arranged within the storage medium and shared by the higher-level processing device; a first means for storing at least one of an access order, an access execution frequency, and an access waiting frequency in access via the first means; and at least one of the access order, the access execution frequency, and the access waiting frequency stored in the first means. a second means for determining the execution priority of the access requests from each of the plurality of access routes, and optimizing the execution order of the access requests from each of the plurality of access routes. A storage device load balance control method characterized by: 2. The storage device according to claim 1, wherein the storage device allocates the reception frequency of the access requests from each of the plurality of access routes based on judgment criteria instructed by each of the plurality of control devices. A storage device load balance control method. 3. Receive priority information for accepting the access requests via the plurality of access routes from the higher-level processing device, and optimize the frequency of acceptance of the access requests from the plurality of access routes based on the priority information. 3. A load balance control method for a storage device according to claim 1, wherein said storage device automatically performs the distribution.