JPH0312768A - I/o controller - Google Patents

Abstract

PURPOSE:To reduce the load of a microprocessor and to improve the throughput of a system by fetching a command via a CRT controller in response to its own executing state. CONSTITUTION:When an MPU 1 carries out a process via a CRT controller CRTC 3, the head address of a command train is written into a register 36. Thus a command control part 37 checks the state of a drawing processor 31 and starts a command fetch part 35. As a result, a memory 2 receives an access and a prescribed command code and its following parameter data are read out to be fetched by an FIFO register of a fetch part 35 via a bus 4. Then these command and parameter are sent to the processor 31. Thus the drawing data is produced and written into a frame buffer 5.

Description

Detailed Description of the Invention [Field of Application on M Beam] The present invention relates to a data transfer technique and a technique that is particularly effective when applied to a command transfer method in a data processing system. This invention relates to techniques that are effective for use in command transfer methods to controllers.

[Prior Art] In a microcomputer system consisting of a microprocessor and I/O devices such as memory, a CRT display device, and a hard disk device, the microprocessor sends commands to a controller such as a CRT controller. When the microprocessor executes the necessary processing, the microprocessor transfers commands directly via the bus.
A common method is to send a command code to the /O controller.

This method is effective when a single command executes a process.

However, when a microprocessor makes a CRT controller with a drawing function draw complex figures,
When executing processing such as filling, it is necessary to transfer multiple chained commands.

Therefore, ■The state of Hitachi HD63484 CRT
The controller configures the system together with the DMA controller, and the microprocessor sets the start address of the command string and the number of commands in the DMA controller before starting it, so that the DMA controller directly sends the command string from the memory to the CRT controller. It is also possible to transfer (``Nikkei Electronics'')
(See May 21, 1984 issue, page 228).

[Problems to be Solved by the Invention] In the above-mentioned command sequence transfer method using the DMA controller, the controllers operate independently of each other, and DMA transfer can only transfer a fixed command sequence, so the I/O There is an inconvenience in that detailed transfer management according to command processing by the controller cannot be performed.

In other words, if the capacity of the command register (F I F○) is exceeded while the DMA controller is transferring a command string to the I/O controller, the transfer may stop, or the next step may be performed depending on the read data, such as in clipping processing. Processing that determines the command cannot be executed by continuous command transfer. In addition, when processing by a microprocessor is required during command processing, such as drawing processing such as filling by a CRT controller, for example, there are problems such as processing being interrupted and unfilled areas occurring.

An object of the present invention is to reduce the burden on a microprocessor when causing an I/O controller to execute a plurality of commands that are chained together, and to improve system throughput.

The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, a register is provided in the I/O controller that allows the address of a command to be set from the outside, or a new command fetch instruction is prepared, and when the address or command fetch instruction is set, the I/O controller automatically reads the command address. It is configured to fetch a command using an address and execute it.

[Operation] According to the above-described means, since the I/O controller fetches commands according to its own execution state, the FIFO
Processing will not be interrupted or undesired processing results will not occur due to the storage becoming full. In addition, for processing where the next command is determined according to the read data, the I/O controller fetches the command itself or interrupts the microprocessor to receive assistance before continuing the processing. This makes it possible to reduce the burden on the microprocessor and improve system throughput.

[Embodiment] FIG. 1 shows an embodiment of a CRT controller to which the present invention is applied and a microcomputer system using the same.

In FIG. 1, 1 is a microprocessor, 2 is a memory in which programs and data are stored, and 3 is a CRT controller, which are connected to each other via a system bus 4. Further, 5 is a frame buffer for storing image data, and 6 is a CRT display device. The frame buffer 5 and the CRT display device 6 are placed under the control of the CRT controller 3.

The CRT controller of this embodiment includes a drawing processor section 3 that generates image data based on commands supplied from a microprocessor 1 and writes it into a frame buffer 5.
1, a display processor unit 32 that reads image data from the frame buffer 5 and displays it on the screen of the CRT display device 6, and a bus interface control unit that connects to the microprocessor to take in commands and data, secure bus occupancy, etc. The CRT controller of this embodiment includes a command fetch section 35 that fetches commands or data into the interface section 33, and a command fetch section 35 that fetches the start address of a command string to be executed by the microprocessor. A configurable command address register 36 and a command control section 37 for controlling command fetching and delivery are provided.

Next, command execution in the above system will be explained.

When the microprocessor 1 causes the CRT controller 3 to execute a certain process, it writes the start address of a command string corresponding to the process into the command address register 36. Command control unit 37 controls command address register 3
When it detects that the address has entered 6, it checks the state of the drawing processor 31 and starts the command fetch section 35. The command fetch unit 35 has a FIFO type register and a bus arbitration function, and after acquiring the right to use the bus, the command address register 36
The address within is outputted onto the system bus 4, and a data read control signal is asserted. Then, the memory 2 is accessed, a predetermined command code and the following parameter data are read out, and are fetched into the FIFO register in the command fetch section 35 via the system bus 4. The fetched commands and parameters are passed to the drawing processor section 31, where the commands are decoded, drawing data such as lines and fills are generated, and written into the frame buffer 5.

When one command processing is completed, the command control unit 37
The command address is incremented by , and the primary command is read from the memory 2 .

As a result of executing a certain command, if the drawing processor 31 cannot process it and the microprocessor 1 needs to process it, the command control unit 37 interrupts the fetching of the next command and sends it to the microprocessor. Generates an interrupt and waits for processing by the microprocessor. At the time of an interrupt, the data to be processed may be passed directly to the MPU via the FIFO in the interface unit 33, or may be written in the memory 2 in advance.

When the interrupt processing by the MPU is completed, the command control unit 37 reads the next command from the memory 2 after receiving the processed command and continues the processing.

Therefore, in this embodiment, the MPU
Even if processing by
Since command fetching continues automatically even if U does not instruct the CRT controller to transfer commands, the load on the MPU is reduced.

Also, since the CRT controller fetches commands by itself depending on the internal state, the FI for command acquisition is
FO does not overflow. Therefore, in the conventional system, the MPU had to monitor the status of the CRT controller in order to prevent FIFO overflow, but in the above embodiment, this is not necessary and the burden on the MPU and software is reduced.

In the above embodiment, when a situation that cannot be processed by the drawing processor occurs, an interrupt is issued to the MPU, but a plurality of the above command address registers 36 are provided in the CRT controller. By setting the start address of the command sequence to be executed in advance in the command address register when such a situation occurs, the CRT controller can continue processing on its own without waiting for interrupt processing. It may be configured as follows.

In the conventional DMA transfer method, only a fixed command sequence can be transferred, so it is not possible to change the command to be executed depending on the data content or processing status. Therefore, there was a risk that the processing would be interrupted midway, but if the above method is followed, highly flexible command transfer becomes possible, which reduces the burden on the MPU and software, and improves the system throughput.

In addition, in the above embodiment, a command address register 36 is provided in addition to the FIFO register for command fetch, but instead of providing a command address register, a new command fetch instruction is prepared, and when this command is received, it is CR using the address sent together
The configuration may be such that the T controller fetches commands into memory.

Furthermore, in the CRT controller of the embodiment shown in FIG. 1, commands can be written directly from the MPU to the FIFO register in the command fetch section 35, and when a command is written directly to the FIFO register, It is also possible to execute the command immediately, and on the other hand, to fetch the command by itself when the address is written to the command address register.

As explained above, in the above embodiment, a register that can set a command address from the outside is provided in the I/O controller, or a command fetch instruction is newly prepared, and when the address or command fetch instruction is set, Since the I/O controller itself fetches the command using that address and executes it, the I/O controller fetches the command according to its own execution status, so the FIFO becomes full and processing is delayed. There will be no interruptions or undesired processing results.

In addition, for processing where the next command is determined according to the read data, the I/O controller fetches the command itself or interrupts the microprocessor to receive assistance before continuing the processing. This has the effect of reducing the burden on the microprocessor and improving system throughput.

Although the invention made by the present inventor' has been specifically explained based on examples, it is to be understood that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist of the invention. Not even.

In the above explanation, the invention made by the present inventor was mainly applied to a CRT controller, which is the background field of application, but the invention is not limited thereto, and can be applied to hard disk controllers and communication LSIs. It can also be used in general I/O devices that operate in response to commands from other microprocessors.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to reduce the burden on the microprocessor when having the I/O controller execute a plurality of commands that are chained with each other, and improve the throughput of the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a microcomputer system using a CRT controller to which the present invention is applied. 1...Microprocessor, 2...Memory, 3
...I/O controller (CRT controller),
4°°...Bus, 33...Interface section, 35
...Command fetch unit, 36...Command address register, 37...Command control unit.

Claims (1)

[Claims] 1. A register is provided whose address can be set from the outside, and when an address is set in the register, data is read from an external memory using the set address according to the internal operating state. An I/O controller configured to perform the following. 2. The I/O controller according to claim 1, wherein the register is separate from a register that takes in commands. 3. It is characterized in that, when a specific command code is supplied from the outside, it is configured to decode it and read data from the external memory using the address associated with the command. I/O controller.