JPH03127825A - Burying method of contact hole - Google Patents

Abstract

PURPOSE:To enable complete burying at the same time even in the case of contacts whose depths of contact are different, by implanting ion in the side wall of a contact hole, and growing wiring member material also from the contact side wall. CONSTITUTION:By using resist 15 which has been used to form a contact hole 16 as a mask, ion is implanted in the side wall of a contact hole 16, and the resist 15 is eliminated. Then wiring member material is selectively buried only in the contact hole 19 by CVD method. By implanting ions in the side wall of the contact hole 16 in this manner, the selectivity of the side wall of the contact hole 16 is removed when the wiring member material is selectively buried in the contact holes by CVD method. Hence the wiring member material is grown from the contact side wall, and complete burying at the same time is enabled even in the case of contacts whose depths of contact are different.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention (i) relates to a method of burying contact holes in a semiconductor integrated circuit.

In conventional semiconductor integrated circuits, as the degree of integration increases, the contact holes become finer, making it difficult to embed LLAI wiring into the contacts using the currently used sputtering method. In order to improve the embedding of this contact, we can taper the contact or use WFe to perform selective CVD using Si reduction, H2 reduction, and 5iHa reduction.
Attempts have been made to embed tungsten into contacts using a method.

Problems to be Solved by the Invention However, improvements by tapering the contact (force exchange, which is effective when the aspect ratio of the contact is small; There is a problem that control is difficult.Also, tungsten selection CVD
C' by law! However, when embedding tungsten into deep contacts, it takes time to embed tungsten, which may result in loss of selectivity.If there are contacts of different depths, if the deepest contact is completely embedded, tungsten will be removed from other contacts. Although there is a problem that the protruding upper layer wiring may be short-circuited, the present invention 41 has been made in view of the above-mentioned problem, and maintains selectivity when embedding the wiring member for deep contacts. It is an object of the present invention to provide a contact hole embedding method that can completely bury contact holes in the same time when different contacts exist.

Means for Solving the Problems of the Present Invention C. Ions are implanted into the side wall of the contact hole using the resist used to open the contact hole as a mask. After removing the resist, wiring members are selectively formed only in the contact hole by CVD. It is something to be embedded.

Effect of the present invention c1 By implanting ions into the side wall of the contact hole, the selectivity of the contact hole side wall is eliminated when selectively embedding the wiring member into the contact hole by the CVD method, so that the wiring member grows also from the contact side wall. It is something to do. In this case, the thickness of the wiring member grown can be reduced to half the contact diameter rather than the contact depth.Contacts with different contact depths can be completely buried in the same amount of time.

Embodiment FIG. 1 shows a process sectional view of the i-th embodiment of the present invention. n
A silicon oxide film (BPSG) containing boron and phosphorus is formed as an insulating film layer on the silicon substrate 11 on which the + diffusion layer 12 and the p+ diffusion layer 13 are formed.
A resist 15 as a contact pattern for the p99 diffusion 13 is formed (FIG. 1(a)). Next, by dry etching using this resist 15 as a mask, BP
Contact hole A1 to p″″ diffusion layer 13 in SG14
6 is opened, and BF2+ is implanted 17 as a p-type impurity into the side wall of the contact hole A16 and the portion exposed by the contact hole of the p11 diffusion 13 without removing the resistor 15 (FIG. 1(b)). At this time, it is preferable to perform the implantation in four steps by rotating the silicon substrate by 90 degrees, for example, so that the ions are implanted uniformly into the side walls of the contact hole. form (
Figure 1 (C)). Next, by dry etching using this resist 18 as a mask, the BPSG 14 is etched with n' diffusion layer 1.
After that, without removing the resist 18, contact hole B19 is opened to contact hole B1.
As'' implantation 20 is performed as an n-type impurity on the sidewalls of 9 and the portions of the n3 diffusion layer 12 exposed through the contact holes (FIG. 1(d)). For example, it is preferable to rotate the silicon substrate 90 degrees each time and perform the process in four steps.
~ Next, the resist 18 is removed, and heat treatment is performed for 30 minutes at 850 degrees in a nitrogen atmosphere, for example, to activate the previously implanted impurities. At this time, the activation heat treatment temperature is BPSG
It is desirable to keep the concentration of boron and phosphorus in BPSG14 at a temperature at which 14 does not flow or ζi at which it does not flow at the activation heat treatment temperature. Tungsten 21 is grown only in the contact hole by selective CVD of tungsten. At this time, tungsten does not grow on the BPSG that is not on the side wall of the contact hole. 21 grows approximately 2 of the contact diameter
Contact hole A16. with one-fold growth film thickness. Contact hole B19 can be filled (Fig. 1(e))
).

FIG. 2 shows a process sectional view of a second embodiment of the present invention. In the first embodiment, the force-pulling described regarding the embedding of the contact between the n3 diffusion layer and the p+ diffusion layer will be explained. The filling of the impurity diffusion layer into the contact will be described. First, the silicon substrate 31
An n-type polycrystalline silicon wiring doped with P at a high concentration (hereinafter referred to as pol
34 (abbreviated as y-3i wiring) is formed.
A BPSG 35 is formed as an insulating film layer. A resist 36 is formed here to open a contact hole (
Figure 2(a)). Next, using this resist 36 as a mask, a contact hole A37 to the n'' diffusion layer 32 and a contact hole B38 to the p○1ySi wiring 34 are opened in the BPSG 35 by dry etching.At this time, the BPSG 35 is flattened by the flow. To be there,
Poly-Si wiring 34 is on top of Si○233 Contact hole A37 is closer to contact hole B
It becomes deeper than 38. After that, without removing the resist 36, the side walls of contact holes A37-B38 and n
As''' implantation 39 is performed as an n-type impurity into the exposed portion of the 4-diffusion layer 32 and the poly-8i wiring 34 through the contact hole (FIG. 2(b)). At this time, ions are uniformly implanted into the contact hole. For example, it is preferable to rotate the silicon substrate by 90 degrees and perform the heat treatment four times at t°C.Next, the resist 36 is removed and heat treatment is performed to activate the previously implanted impurities in a nitrogen atmosphere, for example, at 850°C. The activation heat treatment temperature is the temperature at which BPSG35 does not flow or the temperature at which BPSG35 does not flow.
It is desirable to keep the concentration of boron and phosphorus in G35 at a concentration that does not flow at the activation heat treatment temperature.Finally, for example, selective CVD method of tungsten using a mixed gas of WF6, H2, and Ar as a wiring material. Tungsten 40 is grown only within the contact hole. At this time, carbon tungsten-〇- does not grow on the BPSG that is not on the side wall of the contact hole.The BPSG on the side wall of the contact hole that has been implanted with ions loses its selectivity. Tungsten 40 also grows from the sidewall Contact hole A with a grown film thickness of about 1/2 of the contact diameter and different depths
37, the contact hole B38 can be filled (FIG. 2(C)).

In the first and second embodiments, BFa as the p-type impurity and As as the n-type impurity were used for the ion implantation. B as the p-type impurity and P as the n-type impurity may also be used. Heat treatment for activation of tungsten is performed before selective CVD of tungsten.This heat treatment may be performed after filling the contact hole with tungsten by selective CVD (1. Tungsten 4075<, diffusion layer 33 and poly-8i wiring 34 embedded in
A tungsten silicide layer is formed between the tungsten and the diffusion layer or the poly-3i wiring, resulting in a silicidation reaction with the silicon of the tungsten.
- It also has the effect of improving adhesion. In addition, in the first embodiment, the heat treatment for activating the impurity may be performed separately after implanting the n-type impurity and after implanting the p-type impurity, and the contact openings to the p-type diffusion layer and the n-type diffusion layer are You can do this first.Also, if there is only one of the p-type and n-type diffusion layers, for example, if there is only a p-type diffusion layer, ion implantation of p-type impurities is necessary. Do u
It is possible to carry out the process in the same order as in this embodiment only by not implanting the X and n type impurities.

FIG. 3 shows a process sectional view of a third embodiment of the present invention. n
A resist 45 of a contact pattern for the n' diffusion layer 42 and the p' diffusion layer 43 is formed where the BPSG 44 is formed as an insulating film layer on the silicon substrate 41 on which the 'n' diffusion layer 42 and the p+ diffusion layer 43 are formed. (FIG. 3(a)). Next, using this resist 45 as a mask, a contact hole A46 to the p+ diffusion layer 43 and a contact hole B47 to the n'' diffusion layer 42 are opened in the BPSG 44 by dry etching. However, this contact hole cJ is not completely opened in the diffusion layer 11-, and a BPSG of one-half or less of the contact hole diameter is left below the contact.

Thereafter, without removing the resist 45, for example, Si' implantation 48 is performed on the side walls of the contact hole A4a and the contact hole B47 (FIG. 3(b)). At this time, in order to uniformly implant ions into the side wall of the contact hole, it is preferable to perform the implantation in four steps by rotating the silicon substrate 90 degrees each time. Diffusion layer 42.43
There is no need to cause ion implantation damage to Ll Next
Next, by dry etching using this resist 45 as a mask, the BPSG 44 at the bottoms of contact hole A4a and contact hole B47 are completely etched (
,, exposing the n+ diffusion layer 42 and the p3 diffusion layer 43 (
Figure 3 (C)). Finally, as a wiring material, for example, WFe・
Selection CV of tungsten using H2/Ar mixed gas
Tungsten 49 is applied only inside the contact hole using the D method.
grow. At this time, tungsten does not grow on the BPSG that is not on the side wall of the contact hole. Force = 1
2- BPSG on the side wall of the contact hole implanted with ions
The selectivity is lost. Tungsten 4 is released not only from the bottom of the contact hole but also from the side wall of the contact hole.
9 grows Contact hole A46 and contact hole B47 with a growth film thickness of about half the contact diameter.
can be embedded (Fig. 3(d)).

FIG. 4 shows a process sectional view of a fourth embodiment of the present invention. In the first embodiment, the contact embedding of the (t,n'' diffusion layer and the p'' diffusion layer) was described. We will discuss embedding the high concentration impurity diffusion layer into the contact.
N+ diffusion layer 52 on 1 and P on 5iO2 53 for element isolation.
n-type polycrystalline silicon wiring doped with a high concentration of
Even though the BPSG 55 is formed as an insulating film layer where the ly-3i wiring (abbreviated as ly-3i wiring) 54 is formed, a resist 56 for opening a contact hole is formed there (FIG. 4(a)). Next, this resist 56 is squared = 13
- Take it apart and dry-etch it to BPSG55.
+Contact hole A57 to diffusion layer 52 and poly-
A contact hole B58 to the 8i wiring 54 is opened.

At this time, the contact hole A57 is deeper than the contact hole B58 because the BPSG 55 is flattened by the flow and the poly-3i wiring 54 is located on the 5i0253. However, the deeper contact hole A57? ;! , do not open completely to the diffusion layer, leaving a BPSG of less than half the diameter of the contact hole below the contact. Thereafter, without removing the resist 56, Si implantation 59 is performed on the side walls of the contact holes A37-B38 and the portions exposed by the contact holes of the poly-8i wiring 54 (FIG. 4(b)).
). At this time, it is desirable to perform the ion implantation in four steps, for example by rotating the silicon substrate 90 degrees, so that the ions are implanted uniformly into the side wall of the contact hole. There is no ion implantation damage to the layer 52.Next,
Using the resist 56 as a mask, the BPSG 55 is etched to the 14-n+' diffusion layer 52, and the contact hole A57 is made to reach the diffusion layer (FIG. 4(C)).

Finally, as a wiring member, for example, W Fe, H2, Ar
Tungsten 60 is grown only in the contact hole by a tungsten selective CVD method using a mixed gas of . At this time, the BPSG that is not on the side wall of the contact hole
The BPSG on the side wall of the contact hole that has undergone ion implantation has lost its selectivity.
Tungsten 60 also grows from the side wall of the contact hole Contact hole A57 and contact hole B5 have different depths with a grown film thickness that is about half of the contact diameter
8 can be embedded (see FIG. 4(d)).

In the third and fourth embodiments, Si
Other ions such as AI・B-As-
Even if ions such as P-BF2 are used, the following formula can be used.
In the fourth embodiment, CVD for filling contact holes
As an example of the method, tungsten selection using a mixed gas of WFa, H2, and Ar.・5iH
Examples include selective CVD of tungsten or tungsten silicide using a mixed gas containing a, selective CVD of aluminum, and the like. In addition, in the second and fourth embodiments, Lt, n
I'! for a tp type polycrystalline silicon layer showing an example of simultaneously opening and filling contact holes for a type polycrystalline silicon layer and an n type diffusion layer. ,, it is best to open and fill a contact hole at the same time as the p-type diffusion layer, in which case I
t This can be carried out in exactly the same manner as in this embodiment. Further, the present invention can be easily applied even when forming a contact hole in a single crystal layer formed on an insulating layer. The polycrystalline silicon layer used in the second and fourth embodiments may also have a polycide structure in which a high melting point metal silicide and polycrystalline silicon are laminated; In the same way, the contact hole can be filled.Furthermore, when a high melting point metal layer, etc. exists simultaneously on the silicon substrate, By combining the present invention, contact holes can be reliably filled and highly reliable wiring can be formed.

As described in detail, the present invention eliminates the selectivity of the contact hole side wall when selectively embedding a wiring member in the contact hole by CVD method by implanting ions into the contact hole side wall. The wiring member is made to grow from the side wall as well. This allows contacts with different depths to be completely buried in the same amount of time. Yes
, I) By implanting optimal ions into the type diffusion layer and the n-type diffusion layer and activating them by heat treatment, a reliable contact with low resistance can be formed.

[Brief explanation of the drawing]

Figure 1 shows the process cross-section of the first embodiment of the present invention. Figure 2 shows the process cross-section of the second embodiment. Figure 3 shows the process cross-section of the 7-3 embodiment. It is a process sectional view showing an example.

Claims (1)

[Claims] (1) In a substrate on which at least one of a p-type or n-type diffusion layer is formed, after forming an insulating film layer on the diffusion layer, a resist of a contact pattern for the diffusion layer is formed, and the resist is used as a mask. Opening a contact hole by etching the insulating film layer,
A step of implanting ions that will become a p-type impurity in the case of a p-type diffusion layer and ions that will become an n-type impurity in the case of an n-type diffusion layer into the side wall of the contact hole using the resist as a mask, and removing the impurity by the ion implantation. Contact hole burying method comprising an activation heat treatment step and a step of selectively embedding a wiring member only in the contact hole by CVD method (2) Substrate on which at least one of a p-type or n-type diffusion layer is formed After forming an insulating film layer on the diffusion layer, a resist of a contact pattern for the diffusion layer is formed, and using the resist as a mask, a contact hole is formed at the bottom of the contact and the insulating film layer is formed to be half of the contact diameter. A step of opening the contact hole leaving the following film thickness, followed by a step of implanting ions into the side wall of the contact hole using the resist as a mask, and then etching the insulating film layer at the bottom of the contact using the resist as a mask. A contact hole burying method ( 3) In a substrate having a diffusion layer formed inside a semiconductor substrate and a wiring layer formed on the semiconductor substrate, an insulating film layer is formed on the diffusion layer and the wiring layer, and then the diffusion layer and the wiring layer are formed. forming a resist with a contact pattern corresponding to the contact pattern, opening a contact hole by etching the insulating film layer using the resist as a mask, and implanting ions into a side wall of the contact hole using the resist as a mask; A contact hole burying method comprising a heat treatment step of activating impurities by implantation, and a step of selectively burying a wiring member only in the contact hole by a CVD method.