JPH03130638U - - Google Patents

Info

Publication number
JPH03130638U
JPH03130638U JP4088590U JP4088590U JPH03130638U JP H03130638 U JPH03130638 U JP H03130638U JP 4088590 U JP4088590 U JP 4088590U JP 4088590 U JP4088590 U JP 4088590U JP H03130638 U JPH03130638 U JP H03130638U
Authority
JP
Japan
Prior art keywords
signal
circuit
time division
division multiplexing
audio signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4088590U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4088590U priority Critical patent/JPH03130638U/ja
Publication of JPH03130638U publication Critical patent/JPH03130638U/ja
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)
  • Selective Calling Equipment (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の時分割多重通信装置における
送信部の一実施例の構成を示したブロツク図、第
2図は第1図に示したブロツク図における動作を
説明するための信号波形図、第3図は本考案の時
分割多重通信装置における受信部の一実施例の構
成を示したブロツク図、第4図は第3図に示した
ブロツク図における動作を説明するための信号波
形図、第5図は従来の時分割多重通信装置におけ
る送信部の一例の構成を示したブロツク図、第6
図は第5図に示したブロツク図における動作を説
明するための信号波形図である。 11乃至13……入力端子、3,14……時分
割多重回路、4,15……加算回路、5,16…
…時分割制御信号発生回路、6,17……基準信
号発生器、18,28乃至30……ローパスフイ
ルタ、8,19……FM変調回路、9,20,2
1……アンテナ、22……FM復調回路、23…
…位相同期回路、24……分離パルス作成回路、
25乃至27……サンプルホールド回路、31乃
至33……出力端子。
FIG. 1 is a block diagram showing the configuration of an embodiment of the transmitting section in the time division multiplex communication device of the present invention, and FIG. 2 is a signal waveform diagram for explaining the operation in the block diagram shown in FIG. 1. FIG. 3 is a block diagram showing the configuration of an embodiment of the receiving section in the time division multiplex communication device of the present invention, and FIG. 4 is a signal waveform diagram for explaining the operation in the block diagram shown in FIG. 3. FIG. 5 is a block diagram showing the configuration of an example of a transmitting section in a conventional time division multiplex communication device.
This figure is a signal waveform diagram for explaining the operation in the block diagram shown in FIG. 11 to 13... Input terminal, 3, 14... Time division multiplex circuit, 4, 15... Addition circuit, 5, 16...
...Time division control signal generation circuit, 6, 17...Reference signal generator, 18, 28 to 30...Low pass filter, 8, 19...FM modulation circuit, 9, 20, 2
1... Antenna, 22... FM demodulation circuit, 23...
...Phase synchronization circuit, 24... Separation pulse creation circuit,
25 to 27...Sample hold circuit, 31 to 33...Output terminal.

Claims (1)

【実用新案登録請求の範囲】 オーデイオ信号とオーデイオ信号以外のコード
信号とをそれぞれ異なつたタイミングで時分割多
重するための時分割制御信号発生回路と、前記時
分割制御信号発生回路から得られるそれぞれの前
記制御信号によつて前記オーデイオ信号とコード
信号とを時分割多重する時分割多重回路と、前記
時分割多重回路により時分割多重された前記オー
デイオ信号とコード信号に対し、前記制御信号と
同期したパイロツト信号を加える加算回路と、前
記加算回路より得られた信号によつて搬送波をF
M波に変調するFM変調回路とを具備した送信部
と、 FM波を受信し、FM復調するFM復調回路と
、前記FM復調回路によつて得られた復調信号中
の前記パイロツト信号に同期して前記オーデイオ
信号とコード信号とを分離するためのパルス信号
を生成する位相同期回路と、前記位相同期回路に
よつて得られる前記パルス信号を受けて前記復調
信号より、それぞれ異なつたタイミングで前記オ
ーデイオ信号とコード信号とをサンプルホールド
するサンプルホールド回路とを具備し、前記サン
プルホールド回路によつて、前記オーデイオ信号
とコード信号とを復調生成する受信部からなる時
分割多重通信装置。
[Claims for Utility Model Registration] A time division control signal generation circuit for time division multiplexing an audio signal and a code signal other than the audio signal at different timings, and a time division control signal generation circuit for time division multiplexing an audio signal and a code signal other than the audio signal at different timings; a time division multiplexing circuit for time division multiplexing the audio signal and the code signal according to the control signal; and a time division multiplexing circuit for time division multiplexing the audio signal and the code signal by the time division multiplexing circuit; An adder circuit that adds a pilot signal and a signal obtained from the adder circuit convert the carrier wave to F.
a transmitting section including an FM modulation circuit that modulates the M wave; an FM demodulation circuit that receives the FM wave and demodulates the FM wave; and a transmitter that is synchronized with the pilot signal in the demodulated signal obtained by the FM demodulation circuit. a phase synchronization circuit that generates a pulse signal for separating the audio signal and the code signal; and a phase synchronization circuit that receives the pulse signal obtained by the phase synchronization circuit and generates the audio signal at different timings from the demodulation signal. A time division multiplex communication device comprising: a receiving section comprising a sample and hold circuit that samples and holds a signal and a code signal; and a receiving section that demodulates and generates the audio signal and code signal using the sample and hold circuit.
JP4088590U 1990-04-17 1990-04-17 Pending JPH03130638U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4088590U JPH03130638U (en) 1990-04-17 1990-04-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4088590U JPH03130638U (en) 1990-04-17 1990-04-17

Publications (1)

Publication Number Publication Date
JPH03130638U true JPH03130638U (en) 1991-12-27

Family

ID=31551068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4088590U Pending JPH03130638U (en) 1990-04-17 1990-04-17

Country Status (1)

Country Link
JP (1) JPH03130638U (en)

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