JPH0313595B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a musical tone signal processing device using a digital filter, and is used in electronic musical instruments and other devices having a musical tone generation function. [Prior Art] The use of a digital filter in a timbre circuit of an electronic musical instrument is disclosed in, for example, Japanese Patent Laid-Open No. 59-44096. Conventional digital filters execute filter operations at regular sampling intervals determined by the system.
The filter characteristics obtained were fixed formants. [Problems to be Solved by the Invention] In a conventional tone circuit using a digital filter as described above, when trying to realize the filter characteristics of a moving formant, the filter coefficients must be adjusted according to the pitch of the input musical tone signal. , and a large number of filter coefficients must be prepared. Therefore, the capacity of the filter coefficient storage means becomes large, resulting in a complicated and large-sized device configuration. This invention was made in view of the above points,
It is an object of the present invention to provide a musical tone signal processing device using a digital filter that can realize filter characteristics of a moving formant with an extremely simple configuration. [Means for Solving the Problems] Fig. 1 shows an outline of the present invention, and the musical tone signal processing device according to the present invention uses a pitch synchronization signal that generates a signal PS synchronized with the pitch of a digital musical tone signal. The digital filter circuit 111 receives the digital musical tone signal and executes a filter operation at a sampling period synchronized with the pitch synchronization signal PS generated from the pitch synchronization signal generation means 110.
In FIG. 1, a digital filter circuit 11
The basic structure of an FIR filter is schematically shown in block 1 as an example, and by using the pitch synchronization signal PS as a sampling clock signal with a unit delay D, pitch-synchronized filter operation is performed. Further, according to the present invention, means is further provided for generating a pitch synchronization/asynchronous designation signal for designating whether the filter operation should be performed in synchronization with the pitch of musical tones or asynchronously, and the digital filter circuit 1
In step 11, the filter operation may be executed in either the pitch-synchronized sampling period or a predetermined common sampling period, depending on the pitch synchronization/asynchronous designation signal. [Operations and Effects of the Invention] The sampling period in which the filter calculation is performed in the digital filter circuit 111 is not a fixed period, but a period synchronized with the pitch of the input digital tone signal. The position of the formant in the digital filter is determined based on the sampling frequency. Therefore, if the sampling period of the filter calculation changes in synchronization with the pitch, the resulting filter characteristic will be a moving formant whose formant position changes in synchronization with the pitch. In addition, by switching the calculation cycle of the filter to a pitch-synchronized cycle or a predetermined common cycle using a pitch synchronous/asynchronous designation signal, a moving formant is used during pitch-synchronous operation, and a fixed formant is used during pitch-asynchronous operation. Realized. Therefore, the moving formant and the fixed formant can be easily selected according to the characteristics (for example, timbre) of the musical sound to be realized. Pitch synchronization/
The means for generating the asynchronous designation signal may be any appropriate means such as a tone selection switch, effect selection switch, a dedicated switch, or externally provided performance information data, and is linked to the selection operation of the tone or effect. The filter calculation operation can be switched between pitch synchronization and asynchronous operation based on a dedicated switch operation, or in response to information input from the outside. Therefore, according to the present invention, a moving formant can be realized with an extremely simple configuration in which filter calculation is executed at a sampling period synchronized with the pitch, and the excellent effects of simplicity and low cost can be achieved. In addition, filter calculation operation can be easily switched between pitch synchronization and asynchronous operation, so it is possible to easily switch between moving and fixed formants to match the characteristics of the timbre or the effect imparted to the musical tone that the digital filter is trying to achieve. This has an excellent effect of allowing the change of formants to be performed freely. [Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. <Description of overall configuration of one embodiment> In FIG. 2, a keyboard 10 is provided with a plurality of keys for specifying pitches of musical tones to be generated.
The key touch detector 11 detects a touch applied to a key pressed on the keyboard 10, and may detect either an initial touch or an after touch. Tone selection device 12
consists of a group of operators for selecting the timbre of the musical tone to be generated. The pitch bend operator 13 is for continuously modulating the pitch of the musical tone to be generated in accordance with the amount of operation thereof, and is composed of, for example, a dial type operator. Microcomputer 1
4 includes a CPU (Central Processing Unit) 15, a ROM (Read Only Memory) 16 for storing programs and other data, a RAM (Random Access Memory) 17 for working and data storage, and a data and address bus. 28 to and from each circuit in the electronic musical instrument, processing for detecting pressed keys on the keyboard 10 and processing for assigning sounds of pressed keys to a plurality of sounding channels;
It executes processing for detecting a timbre selection operation in the timbre selection device 12, processing for detecting an operation amount on the pitch vent operator 13, and various other processes. The tone generator 18 is capable of independently generating digital musical tone signals in a plurality of channels, and has a key code KC indicating the key assigned to each channel and a key-on signal KON indicating whether the key is on or off. Other necessary data is received from the microcomputer 14 via the bus 28, and based on this data, digital musical tone signals are generated in each channel. The tone generator 18 includes a pitch synchronization signal generation circuit 19, which generates for each channel a pitch synchronization signal that is synchronized with the pitch of the musical tone signal generated in each channel. In the specifications of this embodiment, the tone generator 18 is connected to the first to sixteenth channels (Ch1 to
A total of 16 channels (Ch16) generate digital musical tone signals in a time-sharing manner. Tone generator 1
Digital musical sound waveform sample value data outputted from 8 in a time-division multiplexed manner is indicated by TDX. The master clock pulse φ generated by the master clock generator 20 controls the basic operating time of the tone generator 18. Time division multiplexing of digital musical waveform sample value data TDX 1
A cycle is 64 periods of the master clock pulse φ, and the time slots for each period in this 1 cycle of 64 periods are numbered from 1 to 64.
As shown in the figure. The figure also shows the specifications of channel timings 1 to 16 of the multiplexed digital musical tone waveform sample value data TDX. For example, the data TDX of the first channel is assigned to four time slots 33-36. In the specifications of this embodiment, the musical sound waveform sample value data TDX is commonly multiplexed and output as data for 16 channels as described above, but the pitch synchronization signals PS1 and PS2 of each channel are divided into two systems. The signals are time-division multiplexed and output every eight channels. One pitch synchronization signal PS1 is the first
- Eighth (Ch1 to Ch8) pitch synchronization signals are time-division multiplexed, and the channel timing is as shown in FIG. Other pitch synchronization signal PS2
is obtained by time-division multiplexing the 9th to 16th (Ch9 to Ch16) pitch synchronization signals, and the channel timing is as shown in FIG. As is clear from the figure, the pitch synchronization signals PS1 and PS2 of each channel
occurs with a width of one time slot, and one cycle of time division multiplexing is eight time slots. Two series adaptive digital filter device (hereinafter sometimes abbreviated as ADF) 21, 22
is a digital filter device configured to be suitable for filtering musical tone signals, and according to the specifications of this embodiment, it is possible to filter musical tone signals for each of eight channels.
1 performs filtering of the musical tone signals of the first to eighth channels, and the other ADF 21 performs filtering of the musical tone signals of the ninth to 16th channels. Inside the ADFs 21 and 22, there is a digital filter circuit of a predetermined type, a filter parameter memory, various circuits that control the supply of filter parameters, and a control that performs filter calculation operation in synchronization with the pitch of the musical tone signal to be filtered. It includes circuits for various functions, such as a pitch synchronization output circuit that outputs a filtered musical tone signal in synchronization with its pitch, and has a configuration suitable for filtering musical tone signals. The digital musical sound waveform sample value data TDX output from the tone generator 18 is ADF21
and 22. Further, the pitch synchronization signal PS1 of the 1st to 8th channels is input to the ADF21, and the pitch synchronization signal PS1 of the 9th to 16th channels is inputted to the ADF21.
2 is input to the ADF22. ADF21 and 22
Now, the data TDX of the channel corresponding to the time slot where the pitch synchronization signals PS1 and PS2 are generated (the signal becomes "1") is internally loaded,
A filter operation is performed on one sample value data of that channel. Therefore, one ADF2
1, a filter operation is performed on the musical tone signals of the first to eighth channels in accordance with the pitch synchronization signal PS1,
The other ADF 22 performs filter calculations on the musical tone signals of the 9th to 16th channels in accordance with the pitch synchronization signal PS2. In this way, the filter operation unit time (signal delay time synchronized with the sampling cycle) in ADFs 21 and 22 is synchronized with the pitch of the musical tone signal to be filtered, and the filter operation unit time changes according to the pitch, so that the filter operation unit time is shifted. Filtering of formant characteristics is realized. In addition, in order to control the basic operation timing of the circuit, the master clock pulse φ and the system synchronization pulse SYNC are connected to ADF21 and ADF22.
given to. As shown in FIG. 3, the system synchronization pulse SYNC is a pulse generated at a period of 64 time slots, and is synchronized with one cycle of time division multiplexing of the digital musical tone signal. Also,
The ADFs 21 and 22 are supplied with various data for controlling filter operations via a bus 28 under the control of the microcomputer 14. Furthermore, in these ADFs 21 and 22, not only is the actual filter calculation operation performed in synchronization with the pitch of the musical tone signal to be filtered, but also the filtered musical waveform sample value data is resampled in synchronization with the pitch. , the output is completely pitch synchronized. The pitch synchronization signals PS1 and PS2 are also used to resample the filtered data in synchronization with the pitch. The digital tone waveform sample value data of each channel outputted from the ADF 21 and 22 is summed by an accumulator 23, and tone waveform sample value data is obtained by summing the sample value data of 16 channels. The output data of the accumulator 23 is converted into an analog tone signal by a digital/analog converter 24, and the signal is generated via a sound system 25. In this embodiment specification, the supply of filter coefficients is controlled in two modes. One is the "static mode", which is a mode in which the filter coefficients are not changed while a musical tone is being produced. The other is the ``dynamic mode,'' which is a mode in which the filter coefficients are changed over time during the period in which musical tones are produced, and the timbre can be changed over time by filtering. Filter coefficients for static mode are stored in filter parameter memories internal to ADFs 21 and 22. The filter coefficients for the dynamic mode are stored in the dynamic control parameter memory 26, which is stored in the microcomputer 1.
The data is read out in a time-switched manner under the control of the ADF 21 and the ADF 22 via the bus 28.
Dynamic/status selection switch 27
is a switch for selecting in which mode the supply of filter coefficients is controlled. An example of the clock frequency is as follows:
The master clock pulse φ is approximately 3.2 MHz, the repetition frequency of one time-division cycle (8 time slots) of the pitch synchronization signals PS1 and PS2 is 400 kHz, and the digital musical sound waveform sample value data
1 cycle of TDX time division (1 cycle in filter)
The repetition frequency of the calculation cycle (64 time slots) is 50kHz. Next, detailed examples of each circuit in FIG. 2 will be explained. <Regarding generation of pitch synchronization signal> FIG. 4 shows an example of the pitch synchronization signal generation circuit 19, which generates pitch synchronization signal PS1 of one system (first to eighth channels). The other pitch synchronization signal PS2 is also generated by the same configuration as in FIG. The pitch synchronization signal PS1 is the P number memory 29
It is generated based on the counter 30 counting the P numbers read out from each channel in a time-division manner. The P number is a number indicating the number of sample points in one cycle of a musical sound waveform having frequencies corresponding to each of the note names C to B in a certain reference octave.
When the pitch synchronization signal PS1 is generated in 8-channel time division as shown in FIG. 3, the basic sampling frequency (in other words, the resolution of the pitch periodic signal PS1) is 1/1 of the master clock pulse φ. 8 frequency (for example, 400kHz), which is common to all pitch names. On the other hand, since the basic sampling frequency is common, the P of each note name is
The numbers each indicate a different value corresponding to the pitch name frequency. If the frequency of a certain note name in the standard octave is fn, and the common sampling frequency (400kHz) mentioned above is fc, then the P corresponding to that note name is
The number is determined as follows. P number = fc÷fn ...(1) Here, the common sampling frequency fc is fc = 400k
Hz, the frequency fn of pitch name A is fn = 440Hz (that is, A4
), then the P number of pitch name A is calculated from the above formula as follows: P number of pitch name A=400000÷440=909. On the other hand, assuming that the number of sample points of different sample point amplitude values per cycle of musical sound waveform that can be generated within the tone generator 18 is 64, the effective sampling frequency fe of the frequency fn is fe = fn × 64 ... (2 ), and when fn=440Hz, fe=440×64=28160Hz. Similarly, the P number and effective sampling frequency fe of each pitch name in a certain reference octave can be determined as shown in the table below. In this case, the standard octave is one octave from note G4 to note F#5.

【table】 In the counter 30 of FIG.
No. PS1 is confirmed based on master clock pulse φ.
Set the common sampling frequency fc to P number.
It can be obtained by dividing the frequency accordingly. From the above
As is clear, the P number is the common sample in one period waveform.
Number of cycles of sampling frequency fc, that is, number of sample points
On the other hand, it can be generated by the tone generator 18.
Effective number of sample points per period of musical sound waveform
is 64 as mentioned above. Therefore, the common sample
The dividing number to divide the programming frequency fc is Frequency division number = P number ÷ 64 ...(3) Then, the divided output is 64 per period of musical tone.
It is possible to obtain 64 pulses, which results in 64 pulses.
All effective sample points can be established.
Ru. The common frequency is determined by the division number determined in this way.
When the sampling frequency fc is divided, the above (1), (2),
From equation (3), fc ÷ Frequency division number = (fn x P number) ÷ (P number ÷ 64) =fn×64=fe……(4) The sample point address is determined by this frequency divided output.
The effective sampling frequency can be adjusted by changing the
number fe can be established. In this way,
The effective sampling frequency fe set is the pitch name frequency
It is in harmony with several fn, and pitch synchronization is realized.
The pitch of each channel generated from the counter 30
The channel synchronization signal PS1 is assigned to that channel.
corresponding to the note name of the key, as shown in equation (4) above.
Divided output signal or effective sampling frequency fe
It is a signal with By the way, the frequency division number determined by the above formula (3) is an integer.
However, it often includes decimals. For example, sound
In the case of name A, Dividing number = 909÷64≒14.20 It is. Therefore, the frequency dividing operation in the counter 30
is 2, which is close to the dividing number determined by equation (3), as described later.
The average result is
The same result as dividing by the frequency division number determined by equation (3) is obtained.
I'm trying to be able to do that. In FIG. 4, the P number memory 29 is
Each note in the standard octave as shown in Table 1
The P number of the name is stored in advance. Each channel
The key code KC of the key assigned to bus 28
is applied to the tone generator 18 via the tone generator 18.
Inside the engine generator 18, the first to eighth
The channel key code KC is the PS1 channel shown in Figure 3.
At the timing shown in Jannel timing.
Divided and multiplexed, key codes for channels 9 to 16
The code KC is the PS2 channel timing in Figure 3.
The signals are time-division multiplexed at the timing shown in .
The first to eighth channels thus time-division multiplexed
key code KC is input to P number memory 29.
be done. The P number memory 29 stores the input numbers 1-
Corresponds to the key code KC note name of the 8th channel.
The P number is read out in a time-division manner. The counter 30 reads from the P number memory 29.
an adder 31 that inputs the output P number;
Select input the output of adder 31 to "0" input
selector 32 and 8 which inputs the output of this selector 32.
Stage shift register 33 and shift register
Gate the lower bit (decimal part) of the output of the
a gate 34 which is applied to the other input of the adder 31;
The upper bit of the output of the shift register 33 (integer
part) and start from 7 bits with all bits being “1”.
An adder 35 that adds all "1" signals consisting of
Contains. The P number itself is a 12-bit binary number.
Although it is a coded signal, the output of adder 31 is
13 bits including 1 extra bit as a signal bit
The signal consists of two signals. Inverted key-on pulse and adder 35 key
The signal output from the output output CO is
It is input to the circuit 36, and this AND circuit 36
The output of is applied to the selection control input of the selector 32.
Addition when the output signal of the AND circuit 36 is “0”
is given from the device 31 to the “0” input of the selector 32.
If the selected signal is selected and is “1”, it is input to “1”.
The given signal is selected. selector 32
The "1" input is under the output of the shift register 33.
digit bit (decimal part) and 7 bits output from adder 35
A 13-bit signal consisting of (integer part) is given.
Ru. Key-on pulse KONP starts when the key is first pressed.
This is a signal that becomes “1” only once, and the signals from the 1st to 8th channels
channels are time-division multiplexed.
Ru. The inverted key-on pulse is this key-on
This is the inverted signal of pulse KONP. Selector 32, shift register 33, adder 3
The part 5 is calculated according to the P number as shown in equation (3) above.
Establish a division number like this, and depending on the integer part of this division number
To divide the common sampling frequency fc using
It is a circuit. The adder 31 calculates the decimal part of the frequency division number.
This is to adjust the value of the integer part according to
be. In the above formula (3), the divisor 64 is 2⁶Therefore, dividing
You can simply calculate the number without doing any special division.
The lower 6 bits of the P number are treated as a decimal part.
It is possible to establish the frequency division number corresponding to the P number simply by
I can do that. Therefore, adder 31, selector 32
and the 13-bit output signal of the shift register 33.
The lower 6 bits are the weight of the decimal part, and the upper 7 bits are the weight of the decimal part.
is the weight of the integer part. The adder 35 adds all “1” signals.
is equivalent to subtracting 1. Therefore, addition
In fact, the output of the shift register 33
1 is subtracted from the integer value of . this adder
The result of subtraction of 35 is the 6 bits of the decimal part that were not calculated.
Return to "1" input of selector 32 along with the current data.
is added to the adder again via the shift register 33.
35. Shift register 33 is the master
Since the shift is controlled by the clock pulse φ,
Therefore, the signal of the same channel is transferred to the shift register 33.
The period output from is the master clock pulse φ.
8 times the period, that is, the period of the common sampling frequency fc
It is the period. At the beginning of the key press, the key is assigned
Inverted key-on pulse at channel timing
KONP becomes “0” only once, and at this time, the
The P number of the key is input via the “0” input of the receiver 32.
is selected. The integer part of this P number is the shift lever.
from the register 33 to the adder 35, and the common sample
1 is repeated from the integer part at the period of the pulling frequency fc
and is subtracted. The subtraction result of the integer part is 1 or more.
When, from the carryout output CO of the adder 35
The carry-out signal “1” is constantly output,
Since the conditions of the AND circuit 36 are satisfied, the selector
32 continues to select the "1" input. Repeated subtraction
Eventually, the output of the adder 35 becomes "0".
In other words, the number of fc equal to the number of integer parts of the P number
When the period has elapsed, the carry-out of the adder 35
The output signal is not output, and the conditions of the AND circuit 36 are satisfied.
It doesn't stand. At that time, the selector 32 inputs "0"
Select P number and output of shift register 33
The sum of the lower 6 bits (decimal part data) of
The output of the calculator 31 is selected. In this way, the decimal part
The P number of the value changed somewhat by the addition is shifted.
P given to the register 33 and now changed
Subtracting 1 from the integer value of the number is repeated.
Ru. Note that the gate 34 is an inverted key-on pulse.
KONP disables it only at the beginning of pressing the key,
At other times, the decimal part data is always sent to the adder 31.
give to For P number in adder 31
The value actually used for frequency division is determined by adding the decimal part data.
The integer value of the frequency division number is the division number found from the P number.
May be 1 greater than the integer value. for example,
The P number of pitch name A is 909, and its frequency division number is
14.20, but initially the minutes are divided according to its integer value 14.
I do a lap, but the next time is 14.20 + 0.20 = 14.40, and
becomes 15.00, and divides the frequency according to the integer value 15.
That's what happens. In this way, it is determined by the P number.
The same as or 1 greater than the integer value of the dividing number.
According to the number, the division of the common sampling frequency fc is
The average result is determined by the P number.
A frequency division operation according to the total frequency division number is achieved. adder
The signal of the carry out output CO of 35 is the frequency division.
This corresponds to the output of inverter 3.
The signal inverted at step 7 is used as the pitch synchronization signal PS1.
Output. To deepen your understanding, let's use pitch name A as an example.
3 shows an example of a change in the output of the vector 32. change time
is the period of the common sampling frequency fc.
Initially, the frequency division number is 14.20, which corresponds to P number 909.
, and then the integer value is decreased by 1, which is 13.20,
Below, 12.20, 11.20, 10.20, ...2.20, 1.20 and so on.
The integer value of is sequentially decreased by 1. In the 14th cycle of fc
The number added to the “1” input of the selector 32 is 0.20.
At this time, the carry out signal becomes “0”.
Then, pitch synchronization signal PS1 becomes “1” and select
The controller 32 selects the "0" input. Selector 3
2 "0" input corresponds to P number 909
Given from shift register 33 at cycle number 14.20
The value 14.40 is given by adding the decimal value 0.20.
Therefore, 14.40 is output from the selector 32.
After that, the output of selector 32 is 13.40, 12.40,
11.40, ...2.40, 1.40, decreasing by 1 in sequence.
Then, in the 14th cycle of fc, the input to “1” of selector 32
When the added value becomes 0.40, the key of adder 35
The Yariout signal becomes “0” and the pitch synchronization signal
No. PS1 is generated. At this time, the output of adder 31
The force is 14.20 + 0.40 = 14.60, which is the selector
to the shift register 33 via the “0” input of 32.
Given. Thus, in the case of pitch name A, 14 or 15
The frequency is divided using the dividing number, and the common sampling
Every 14 or 15 cycles of frequency fc (e.g. 400kHz)
The pitch synchronization signal PS1 becomes "1". The pin corresponding to the other 9th to 16th channels
The Tuchi synchronization signal PS2 is also generated in the same manner as described above.
Ru. <Description of tone generator> In the tone generator 18, as described above,
Pitch synchronization signal of each channel generated by
Use PS1 and PS2 to find the exact musical tone that should be generated.
according to sampling timing synchronized with
A musical tone signal can be generated. Of course
However, this is not limited to,
Generates musical tone signals according to pulling timing
It is also possible to do so. Sample point address (instantaneous position) of the musical tone to be generated
The address data that specifies the phase angle) is
Pitch synchronization signals PS1 and PS2 of each channel
This is caused by counting each independently.
I can do it. However, pitch synchronization signals PS1, PS
2 is the reference octave (G4 to F#5 notes) mentioned above.
Since it is compatible with Pitzchi, the above address data
, the octave of the musical note that should be generated
The above pitch synchronization signals PS1 and PS2 are adjusted according to the sound range.
It is necessary to switch the count rate when counting.
be. For example, an octave tone from G3 to F#4.
When generating, pitch synchronization signals PS1, PS2
Count 0.5 each time G4~F#5 occurs.
When generating octave musical tones, use pitch synchronization.
Counts 1 every time signals PS1 and PS2 occur
and generates musical tones in the octave from G5 to F#6.
In this case, pitch synchronization signals PS1 and PS2 are generated.
Count 2 each time. In this way, the ease that should occur
Acoustic sound that changes in sync with the pitch and octave of the sound.
Address data is generated for each channel and this address data is generated for each channel.
Generates digital musical tone signals based on dress data
do. Musical tone signal generation in tone generator 18
Any method may be used. for example,
Store it in the waveform memory according to the address data above.
A method for sequentially reading out musical sound waveform sample value data
(memory read method) or the above address data
A predetermined frequency is set as phase angle parameter data.
Executes modulation calculation to generate musical waveform sample value data.
The desired method (FM method) or the above address
data as phase angle parameter data.
Execute width modulation calculation to generate musical waveform sample value data
What are the known methods such as the AM method?
Other methods may also be used. In addition, the memory read method
When using , the musical sound waveform to be stored in the waveform memory.
may have only one period waveform, but it may be a multi-period waveform.
A shape is preferable because it can improve the sound quality.
Store multiple period waveforms in waveform memory and read them
For example, the method shown in JP-A-52-121313 is
The entire waveform from the start to the end of the sound can be memorized.
A method of reading the data once, or a method of reading out the
Multiple cycles of attack part as shown in issue 142396
Store the waveform and one or more periodic waveforms of the sustain part, and
After reading the waveform of the tact part once, the waveform of the continuous part
A method of repeatedly reading out the
Discrete sampling as shown in issue 147793
Save multiple waveforms and read out the waveform at any time.
Repeat the specified waveform by switching sequentially in between.
Various methods are known, such as a return read method.
These may be adopted as appropriate. <Preliminary explanation of adaptive digital filter
＞ The basic calculation format for digital filters is
Generally, finite impulse response (FIR) filters and
There is a limited impulse response (IIR) filter.
Adaptive digital filter implementation in this example
FIR filters are used in locations 21 and 22.
There is. First, a general explanation related to FIR filters.
conduct. (a) Basic circuit configuration of FIR filter Figure 5 is a basic circuit diagram of an FIR filter.
Therefore, x(n) is the digit of any nth sample point.
This is the drum sound waveform sample value data, and the FIR
This is the input signal of the filter. z^-1is unit time delay
is a time delay of one sampling period.
This is to set. Therefore, x(n-1)
is the digital musical sound wave at the n-1st sample point
It is sample value data of the form x(n-N+1)
is the digital music of the n-N+1st sample point
This is sound waveform sample value data. N is Impul
is the duration of the response and the order of the FIR filter
corresponds to h(0) to h(N-1) are Nth order frames.
is the filter coefficient. This filter coefficient is entered
The triangular blocks shown are multiplicative elements, and the delayed
Data x(n) for each sample point delayed by the element
The corresponding file for x(n-N+1)
Multiply the router coefficients h(0) to h(N-1). Squared
Blocks with a + sign in which calculation power has been input are
It is an addition element, which adds and sums the output of each multiplication and outputs
Obtain the force signal y(n). Impulse response of such a FIR filter
The z-transform or transfer function of {h(n)} is H(z)＝_N-1 〓ⁿ⁼⁰ h(n)z^-n =h(0)+h(1)z^-1+...h(N-1)z^-(N-1)
……(Five) It is expressed as (b) Linear phase characteristics of FIR filter One feature of such FIR filters is that
It is possible to make the phase characteristic a linear phase.
Ru. Assuming linear phase, the input and output waveforms of the filter
The phase corresponds completely with linear characteristics between
However, no distortion occurs in the output waveform. Therefore, it is easy
Filter processing of signals such as sound, voice, audio, etc.
suitable for Linear phase FIR filter smell
Then, the phase characteristic is expressed as a function of the angular frequency ω. θ(ω)=−αω ……(6) It is required that Here α is the phase delay
It is a constant called . Also, the direct
Necessary and sufficient conditions for an FIR filter with linear phase characteristics
The impulse response is as shown in equation (8) below.
symmetrical, and has a phase delay α as shown in equation (7) below.
uniquely depending on the duration time (filter order) N
It is to be stipulated. α=(N-1)/2...(7) h(n)=h(N-1-n)...(8) However, 0≦n≦N-1 (c) Symmetry of filter coefficients As shown in equation (8) above, the impulse response exhibits symmetry.
Having filter coefficients h(0) to h
(N-1) means that it has symmetry. vinegar
In other words, setting the filter coefficients with symmetrical characteristics
By this, the linear phase characteristics mentioned above can be realized.
This is possible. Impulse response illustrates an example of symmetry
If the order N is an odd number, it is as shown in Figure 6.
When N is an even number, the result is as shown in FIG. figure
As is clear from
It exhibits symmetrical properties. If N is an odd number,
(N-1)/quadratic is the center, and the images on both sides of it are
The impulse response becomes symmetrical. If N is an even number
is centered between (N-2)/quadratic and N/2.
and the impulse responses on both sides are symmetrical.
Ru. The filter coefficients for orders in symmetrical positions are
Since they are the same value, all filter coefficients of order N
You don't need to prepare that many, just half that number. Details
In other words, if N is an odd number, from the 0th order to (N-
1)/{(N-1)/2}+1 frames up to second order
All you need to do is prepare the filter coefficients, {(N-1)/
2} The filter coefficients from +1st order to N-1st order are
Symmetry from 0th order to {(N-1)/2}-1st order
You can use the filter coefficients at the location. sand
In other words, the same filter coefficient is used for the 0th order and the N-1st order.
The same filter is used for the 1st and N-2nd order.
Use numbers. Also, if N is an even number, the 0th order
N/2 files from (N-2)/2nd order
All you need to do is prepare the coefficients, from N/2 to N-1
The filter coefficients from 0th order to (N-2)/
Use filter coefficients at symmetrical positions up to the second order
do it. (d) Frequency response of linear phase FIR filter The impulse responses are matched as shown in Figures 6 and 7.
Frequency response of linear phase FIR filter exhibiting symmetry
H^*(e^jFigures 8 and 9 illustrate the characteristics of 〓).
It seems like. If N is an odd number, as shown in Figure 8.
ω=π (where π is the sampling frequency fs
1/2), the level is fixed at 0.
It is not specified and can be set arbitrarily. If N is an even number
As shown in Figure 9, the level when ω = π is necessarily
Z becomes 0. As is clear from this, the order N
If is an odd number, depending on the filter coefficient settings
It is possible to realize high-pass filter characteristics.
However, if N is an even number, the high-pass filter
It is impossible to realize sexuality. However, N
If is an even number, it is easier to design the filter, and the low-pass
Suitable for designing filters and bandpass filters
ing. Therefore, depending on the filter characteristics you are trying to achieve,
so that the order of the filter N can be switched between even and odd.
It is preferable that the adapter of this embodiment
In the digital filter devices 21 and 22
can perform such even-odd switching of order N.
The specifications are such that it can be done. i.e. van
Filter characteristics of high-pass filter and low-pass filter
When performing filtering, set the order N to an even number.
and filtering with high-pass filter characteristics.
If so, set the order N to an odd number. (e) Other features of FIR filter Other features of FIR filters include
Good stability as there is no back loop
There is a characteristic that In other words, the feedback filter, like an IIR filter,
If there is a loop, problems such as oscillation will occur.
However, FIR filters do not cause problems such as oscillation,
It is also easy to design. In addition, when changing the filter characteristics over time,
FIR filters are also advantageous in these cases. this
In the case of temporally different filter characteristics,
Prepare a set of filter coefficients corresponding to each
but then the filter characteristics
A large number of filter coefficients are used to refine the time fluctuations of
A set of is required. To solve this problem
In order to
Prepare the coefficients and calculate between the two sets of filter coefficients.
By performing interpolation, the time elapsed between
to generate a dense set of filter coefficients, and thus
time by the filter coefficients generated by interpolation.
It is possible to set filter characteristics that change over time.
Conceivable. Interpolating the filter coefficients like this
Achieving time-varying filter characteristics while performing in real time
If so, use a highly stable filter like an FIR filter.
In some cases, the filter coefficients are modified to account for instability.
It is very advantageous because there is no need for a husband. In addition, the signal word in the digital filter
Since the length is finite, the signal within the limited word length
Data must necessarily be rounded. like this
The rounding causes noise, but the FIR file
There is no feedback loop in data, so rounding
Since the error due to noise is not accumulated,
This is advantageous in terms of countermeasures. Furthermore, the various characteristics of the FIR filter as described above
For example, the book ``Theory and
Application of Digital Signal Processing”
(Authors: Lawrence, R. Rabiner; Bernard,
Gold, Publisher: Prentice-Hall Inc)
It is described in detail. Next, the adaptive date in this example is
In the digital filter devices 21 and 22,
Some of the features will be briefly explained in advance. (f) How to find filter coefficients Filter coefficients are used to analyze actual musical tones.
More demanded. to find the filter coefficients
An example of the procedure will be explained with reference to FIG.
First, we will introduce two types of musical sound waveforms (original) that represent different tones.
Sampling musical sound waveforms from natural instrument sounds
Prepare by doing so. For example, the original sound waveform 1 is
This is the waveform of a piano sound played with a strong key touch.
The original sound waveform 2 was played with a weak key touch.
This is the waveform of a piano sound. Next, the fast Fourier transformation
The Fourier components of the original sound waveforms 1 and 2 are
Analyze and based on this, the spectrum of both waveforms 1 and 2
Find the characteristics of the file. Next, the spectrum of waveforms 1 and 2
Find the difference in the characteristics of the Next, the spectral characteristics of the difference
quantize the filter coefficients and calculate the filter coefficients based on this.
process. The last obtained filter coefficient is
Store in memory. A filter that realizes time-varying filter characteristics
The data coefficients are parameter memory for dynamic control.
26 (Figure 2) and does not change over time.
Filter coefficients that achieve steady filter characteristics
is a parameter in ADF22 and 22 (Figure 2).
stored in the data memory. In addition, in the above, the spectral characteristics of the difference between the two waveforms are
The reason for determining the filter coefficients based on the tone difference is
One of the original music waveforms in the energator 18 (Fig. 2)
(for example, the waveform corresponding to a strong key touch)
A musical tone signal is generated, and a difference space signal is generated.
filtering according to the vector characteristics.
the other original sound waveform (for example, for weaker touches).
to obtain a musical tone signal corresponding to the corresponding waveform).
This is to do so. Filter according to key touch
When performing key touch strength,
Prepare a corresponding set of filter coefficients.
of the filter coefficients corresponding to several stages.
Prepare only the set of keys, and then use the keys that are not prepared.
The filter coefficient corresponding to the Tsuchi strength is the same as above.
It may also be determined by interpolation. Of course, only the filter coefficient corresponding to the key touch
However, the pitch (or range) or type of tone
or other various factors.
The data coefficients are prepared using a method similar to that described above. (g) Filter operation synchronized with pitch Each service in ADF21 and 22 (Figure 2)
The filter calculation timing for each sample point is accurate.
It is set by synchronization signals PS1 and PS2.
This means that the unit time delay in filter operation is
(z in Figure 5)^-1) is the pitch synchronization signal PS1, PS
2. Sunawa
Sampling frequency in filter operation
fs is set by pitch synchronization signals PS1 and PS2
be done. Specifically, it corresponds to each note name G~F#
The frequencies of the pitch synchronization signals PS1 and PS2 are as described above.
Same as the effective sampling frequency fe shown in Table 1.
Since they are the same, the fencing in ADF21 and 22 is
The sampling frequency fs of the filter operation is
As shown in the table, depending on the tone name of the musical tone signal
It will be different. Sun in filter operation
The pulling frequency fs is shown in Figures 8 and 9.
Corresponds to ω = 2π in the frequency response characteristic like
do. As is clear from this, depending on the note name
When the sampling frequency fs changes, the frequency response
The frequency corresponding to ω=2π in the response characteristic is also
The result will change depending on the
The router characteristic becomes a moving formant characteristic. this
The moving formant characteristics are the timbre of the musical signal.
It is very suitable for control. In contrast, the sample in filter operation
The switching frequency remains constant regardless of the pitch of the input signal.
, the resulting filter characteristics are fixed filters.
Becomes Ormanto. (h) Pitch synchronous/asynchronous switching As mentioned above, the moving formant filter is
Suitable for controlling the timbre of musical sounds, but trying to obtain
Depending on the tone or effect, a fixed formant may be used.
Iruta may be preferable. Also, Pitsu
Occurs when operating the Tivent controller 13 (Fig. 2)
Fixed even when the pitch of the sound is greatly slid.
Formant filters are preferred. the
Therefore, in ADF21 and 22 of this embodiment,
Perform filter operations in pitch synchronization or asynchronously
It is designed so that it can be switched between
Ru. In addition, such pitch synchronization/asynchronous switching
Replacement is not the same for all channels, but for each channel.
Specify pitch sync or async independently for each file.
It has become possible to do so. By the way, when operating the pitch vent, the fixed foil is
The reason why a cloak filter is preferable is as follows.
That's right. Pitch vent operator 13
Pitch control can only be used to control slight pitch deviations.
Large pitch slide control over several pitches
is also possible, in which case the sounds shown in Table 1 above
Pit across the octave boundaries of G~F#
control may be applied. At that time, Pitsu
If you are performing filter operations synchronized with
The pulling frequency fs fluctuates rapidly and
The cutoff frequency also fluctuates rapidly (moving focus
), it also causes unnatural timbre changes.
Tarasu. For example, the sound generated by pitch vent operation
The musical note in the note slides from F#5 note to G5 note.
If the sampling frequency is 47.359kHz
to 25.088kHz (see Table 1 above).
) In the case of moving formants, the difference is the same as
The cut frequency also fluctuates rapidly. This way
To prevent such inconvenience, when operating the pitch vent,
Moving formant (filter synchronized to pitch)
fixed formant (in pitch) without using
Asynchronous filter operation) is preferable. Pitsu
In case of asynchronous filter operation, ADF21 and
Sampling frequency of filter operation in and 22
The wave number is 50kHz in the example shown in Figure 3. (i) Files according to dynamics/status
Switching the data order As mentioned above, in dynamic mode
is executed by a microcomputer in real time at the time of pronunciation.
Dynamic control parameters under the control of 14
Dynamic control from the data memory 26 (Figure 2)
Read the parameter data for the ADF
21 and 22.
Therefore, data transfer time is limited and file transfer time is limited.
If the order of the router coefficients is large, within a limited time
Transfer filter coefficient parameter data of all orders
There is a possibility that it cannot be done. Therefore, the dynamic
The filter order in mode is real time data.
The order must be limited to match the transfer time.
Must be. On the other hand, in static mode,
Since there is no need to change the filter coefficients,
There are no such problems. Also, the filter order is large.
It is possible to achieve very fine filter characteristics.
It is preferable because Therefore, static mode
In this case, the filter order should be made sufficiently large.
I have to. For the above reasons, the specifications of this example
is dynamic mode or static mode.
The filter order can be changed depending on the
There is. For example, when in static mode,
The filter order is set to 32 (however, this is for even-order characteristics).
and in the case of odd-order characteristics, it is 31st order),
Set the filter order in dynamic mode.
The 16th order (15th order for odd-order characteristics) is half of
ing. (j) Weighting control of filter coefficients Binary digital data of one filter coefficient
The format is a 12-bit filter coefficient data section,
It consists of a 3-bit weighting data part. 3bi
The weighting data part of the tuto is 0, +1, +2, +
6 types of shift amounts: 3, +4, and +5 bits
This shift
The filter coefficient data section is shifted according to the amount.
and the weighting is done. 12-bit file
The router coefficient data part can be shifted by up to 5 bits.
By performing weighting control, the filter
The dynamic range of numbers is effectively 17 bits.
Expanded. This kind of weighting control
While ensuring sufficient dynamic cleansing,
Number of bits of filter coefficient stored in memory
The capacity of the filter coefficient memory is
Helps save on quantity. <Overall explanation of adaptive digital filter> Figure 11 shows the addresses corresponding to channels 1 to 8.
Adaptive digital filter device (ADF) 2
1 is a block diagram schematically showing an example of the internal configuration of
The other ADF22 can be configured in exactly the same way.
can. The input interface 38 is a tone generator
The pitch synchronization signal PS1 is received from the
input the pitch synchronization signal PS1 of each channel.
Condition adapted to the calculation timing inside ADF21
A detailed example is shown in Figure 12.
is shown. The timing signal generation circuit 39 is inside the ADF 21.
Generates timing signals that control various operations of the unit.
At the same time, input from the input interface 38
corresponds to the pitch synchronization signal of each channel.
Performs various operations required for filter operation based on signals.
It generates a calculation timing signal, and its details are
A detailed example is shown in FIG. As mentioned later
The filter operation for each channel is performed in a time-sharing manner.
This timing signal generation circuit 39
filter performance of each channel at the appropriate time.
Give a timing signal to control the calculation operation.
It's getting old. State memories 40, 42 and multipliers and
The humulator parts 41 and 43 are filters of the FIR filter.
A digital filter circuit that performs filter calculations.
Ru. State memory 40, multiplier and storage
A digital filter circuit consisting of a data section 41 (this
This is called an A-series digital filter circuit).
1st to 4th channel (Ch1 to Ch4) files
State memory 42 and multiplier
and an accumulator section 43.
filter circuit (this is a B series digital filter
(referred to as circuit) is the fifth to eighth channel (Ch5~
Ch8) is used to perform the filter operation. Each series
The digital filter circuits A and B each have 4 channels.
The filter operation for the filter is performed in a time-sharing manner.
It's getting old. Filters for channels 1 to 8
Reason for dividing calculation into two series A and B
is due to circuit design reasons. state memory 4
0,42 is tone generator 18 (Figure 2)
The digital musical tone signal sample value data given by
Import data TDX in synchronization with pitch synchronization signal PS1
the number of stages corresponding to the predetermined filter order.
Delayed at the timing corresponding to the Tuchi synchronization signal PS1
The basic circuit of the FIR filter shown in Figure 5 is
unit delay element z in^-1corresponds to the set of Squared
The calculator and accumulator sections 41 and 43 are
Digital musical tones delayed in memory 40, 42
For signal sample value data, its delay order is
Multiply the filter coefficients of the corresponding orders, and
The calculation results are cumulatively summed, and the FIR shown in Figure 5
Multiplication elements and addition elements in basic filter circuits
corresponds to Multiplication with A-series state memory 40
A detailed example of the container and accumulator section 41 is shown in Fig. 14.
The structure of the B series is similar to this.
can be achieved. The microcomputer interface 44 is a microcomputer
data and access under the control of the user 14 (Figure 2).
Various data given via the address bus 28
Accepts and supplies to each circuit in ADF21.
be. Accepted via this interface 44
The types of data that can be collected are as follows. Key code KC: assigned to each channel
Show the key. Key-on pulse KONP: Assigned to each channel
The signal becomes “1” only once at the beginning of pressing the key.
Ru. Touch code TCH: Assigned to each channel
Indicates the strength of the touch when pressing the key. Tone code VN: assigned to each channel
Displays the tone type (voice) selected for the key.
show. The above KC, KONP, TCH, and VN are specified times and minutes.
According to the division timing, each channel is divided into hours and minutes.
output from the interface 44 in a partially multiplexed state.
parameter processing unit
(Sometimes called PPU) It is given to 45. Pitch synchronous/asynchronous designation signal PASY: This
Digital filter calculation in ADF21
A signal that specifies whether to perform the process synchronously or asynchronously.
This is the number. This signal PASY is also
can be given in splits, and the file
Pitch synchronous/asynchronous control of data calculations on each channel
It can be done independently for each. This signal PASY
is the selected tone type or pitch vent.
Operation details of the operator 13 (Fig. 2) or dedicated
Or, it may occur depending on the operation status of the appropriate controls, etc.
and is provided to interface 44 via bus 28.
It will be done. Pitsu output from interface 44
The synchronous/asynchronous designation signal PASY is input interface
is applied to the pitch synchronization signal PS1.
The input interface 38 generates a signal according to the
It is used to control whether or not to Dynamic filter parameter DPR: Ma
Dynamite under the control of Microcomputer 14
read from the parameter memory 26 (Fig. 2) for
Extracted filter parameters (filter coefficients)
It is. As mentioned above, for this dynamic mode
The content of the filter parameter DPR is the duration of the sound.
Changes over time. This dynamic mode
The data format of the filter parameter DPR for
Similarly, the 12-bit filter coefficient data part and 3
It consists of a bit weighting data part, and further the following
Contains data that identifies whether a number is even or odd. Also, the aforementioned
As per the filter parameters for this dynamic mode.
The order of one set of data DPR is 16th (or 15th).
Ru. Furthermore, as is clear from the above, the linear phase characteristic
Due to the symmetry of the filter coefficients in
A set of dynamic mode filters to prepare
The parameter DPR only needs to be for the 8th order. Dynamic/static selection signal DS:
Power/status selection switch 27 (No.
This is a signal generated in response to the operation shown in Figure 2), and is a signal generated in response to the operation of
Is the filter calculation performed in the dynamic mode described above?
Instruct whether to perform in static mode. The above DPR and DS are parameters from interface 44.
is applied to meter selector 46. The parameter memory 47 is in static mode.
Filter parameters (filter coefficients) for
It is something I have memorized. The parameter processing unit 45 is
From parameter memory 47 for static mode
It functions to read the filter parameters of. vinegar
That is, given a key-on pulse KONP
, tone code VN, touch code TCH, key
Parameters to be read based on the contents of code KC
Calculate the address of the data memory 47 and use this address.
The filter parameters stored in the memory
Read from 47. State spider read out
The filter parameter SPR for the
46. This state spider
The data format of the filter parameter SPR for
This is similar to the DPR described above. Also, as mentioned above,
Filter parameter SPR for vertical mode
One set of orders is 32nd (or 31st). Furthermore, before
As is clear from the above, the curve in the linear phase characteristic
Due to the symmetry of the filter coefficients, a set of actually prepared
Filter parameters for static mode
Only the 16th order is sufficient for SPR. The parameter selector 46 is a dynamic/speed
dynamically depending on the contents of the vertical selection signal DS.
File for static mode or static mode
Select one of the parameters DPR and SPR. Selection
The selected parameters are A series and B series parameters.
The data is input to data supply circuits 48 and 49. A series
In the parameter supply circuit 48, the first to fourth channels
Accepts the filter parameter DPR or SPR of the file
This is stored and used at the same time as the filter calculation timing.
The state memory 40, multipliers and
It is supplied to the mulrator section 41. B series parameters
In the supply circuit 49, the films of the fifth to eighth channels are
Do the same thing for the data parameters. Filter parameters for static mode
SPR is a parameter memo only once at the beginning of key press.
The parameters are read out from the library 47 and then supplied
It is stored in circuits 48 and 49. Therefore, the state
In Tsuku mode, the filter coefficient is set during the sound generation period.
does not change and maintains constant filter characteristics. other
On the other hand, filter parameters for dynamic mode
DPR allows new parameters to be installed on the microcontroller.
parameters until given via the interface 44.
stored in the data supply circuits 48 and 49, and
The content of the parameter DPR changes over time.
It is rewritten every time. Output from parameter supply circuits 48 and 49
Identify whether the order of filter parameters is even or odd
Odd-even identification data EOA1 to EOA4, EOB1 to EOB
4 is given to state memories 40 and 42, and
router coefficient data section COEA, COEB and weighting data
The data parts WEIA and WEIB are multipliers and storage units.
The data is given to the data sections 41 and 43. In addition, the marks in the diagram
The suffix A or B in the number indicates the distinction between A series and B series.
represents something different. Data EOA1~EOA4, EOB1~
EOB4 is given in parallel for each channel.
However, data COEA, COEB, WEIA, WEIB
is given for each channel in a time-sharing manner. Parameter processing unit 45, parameter
parameter selector 46, parameter memory 47,
A detailed example of the meter supply circuits 48 and 49 is shown in Figure 15.
It is shown. The pitch synchronization output circuit 50 includes a multiplier and an
Each channel output from the mulrator sections 41 and 43
filtered musical tone signal sample value data.
input and synchronize these to each pitch.
This is a circuit that re-samples the signal by sampling. Click here
The signals used for sampling control are
source 38. Pitch synchronization signal PS1D
This is the pitch synchronization signal for each channel.
PS1 is delayed by a predetermined time. in a pinch
Delayed pits due to synchronized resampling
The reason for using the synchronization signal PS1D is because the data in the previous stage is
Musical tone of each channel in digital filter calculation
This is to match the time delay of the signal. like this
The digital filter output signal is synchronized to that pitch.
The process of resampling after
The frequency is harmonized to the pitch of the musical note, so there is no folding noise.
solve the problem of issuance. Daiji in sync with Pitzchi
When performing digital filter calculation, use digital filter.
The router output signal has a sampling frequency synchronized to pitch.
Since it has a period of time, a pitch synchronization output circuit 50 is specially provided.
Even if you do not have one, it is possible to achieve pitch synchronization.
Digital filter performance is performed asynchronously to the pitch.
When performing calculations, pitch synchronization is required.
A synchronous output circuit 50 is required. pitch synchronization
A detailed example of the output circuit 50 is shown in FIG.
Ru. Next, the adaptive digital filter device 21
A detailed example of each part will be explained. In addition, in each figure, "1D" is written in the block.
Circuits marked with a number such as “8D” and the letter D are slow
It is a delay circuit or shift register, and the previous number
indicates the number of delay stages or stages. Also, this
in the delay circuit or shift register block.
delay control clock pulse or shift control clock pulse.
It is not shown that the Tsuku pulse is input.
The master clock pulse φ (see Figure 3)
Delay or shift control is performed by. <Input interface 38: Figure 12> In Figure 12, the pitch synchronization signal PS1 is
to the shift register 53 via the circuits 51 and 52.
is input. As shown in Figure 3, this pitch synchronization
Signal PS1 has 8 time slots as one cycle.
8 channels are time-division multiplexed, or
Synchronize to the pitch of the key assigned to the channel.
1 time slot corresponding to that channel with a period of
A signal "1" is generated at the point. shift register 53
The output of is passed through an AND circuit 54 and an OR circuit 52.
It is returned to the input side, and the pitch synchronization signal for 8 channels is sent back to the input side.
No. PS1 is in the 8-stage shift register 53.
Retained in circulation. Eight channels corresponding to each channel.
A latch circuit 55 is provided in parallel, and a shift circuit 55 is provided in parallel.
The pitch synchronization signal output from the register 53 is
The data input D is inputted in parallel. Each rat
Each channel is connected to the latch control input L of the latch circuit 55.
Latch timing signal φFS1 (25) corresponding to
φFS2 (29), ...φFS8 (56) can be input and left respectively.
The number written after φFS indicates the channel number.
The next number in brackets is one operation cycle.
(64 time slots shown in Figure 3)
indicates the slot number and corresponds to that time slot number.
the latch timing in the corresponding time slot.
The signal becomes “1”. For example, signal φFS1
(25) becomes signal “1” at time slot 25,
This corresponds to the first channel. Figure 3
As is clear from reference, time slot 25 is
The first channel of pitch synchronization signal PS1
It supports time division timing. Therefore, this
Latch controlled by signal φFS1 (25)
The pitch synchronous signal of channel 1 is connected to the circuit 55.
Contents of issue PS1 (at the timing of synchronization with Pitzchi)
is the signal “1”, and the signal is “1” at other times.
“0”) is latched. Other channels 2 to 8 as well
The pitch sync signal of each channel is
each in parallel to the latch circuit 55 at a certain timing.
Latched. In addition, the latch timing corresponding to each channel
The input signals φFS1 (25) to φFS8 (56) are the same as those shown in Figure 13.
generated from coder 56. The decoder 56 is
The output of the printer 57 is decoded and various types of
generates a timing signal. Counter 57 is a master
The modulus 64 that counts the lock pulse φ
counter and system synchronization pulse SYNC
(FIG. 3). each
Latch timing signals corresponding to channels 1-8
Which time slot are numbers φFS1 (25) to φFS8 (56)?
It is clear from the display in Figure 13 that this occurs in
cormorant. Returning to Figure 12, each timing signal φFS1 (25)
~φFS8 (56) is multiplexed and inverted by the NOR circuit 58.
be transferred. The output of the NOR circuit 58 is the AND circuit 54
is input. This causes the latch circuit 55 to
Shift rate for the channel where the acquisition was performed
The memory of register 53 is cleared. On the other hand, the pitch synchronization signal PS1 became “1”.
It is latched in the latch circuit 55 corresponding to the channel.
The received signal “1” will correspond to it in the next cycle.
Latch timing signal φFS1 (25) to φFS8 (56)
is held until it occurs. In this way, the latch times
The pitch synchronization signal PS1 is “1” on the line 55.
Supports 64 time slots for channels
The signal "1" is held for a period of time. Each chiyanne
The output of the latch circuit 55 corresponding to the filter
The timing shown in Fig. 13 is used as the calculation request signals φF1 to φF8.
is applied to the switching signal generation circuit 39. I'll explain later
In other words, these filter operation request signals φF1 to φF8 are
When it becomes “1”, the filter performance for one sample point is
calculation is performed. Pitch synchronization signal PS1 is generated.
Only when the filter operation request signals φF1 to φF8 are
Since it becomes “1”, it is easy to apply a filter after all.
Digital filter performance synchronized to the pitch of the sound signal
A calculation will be performed. For example, as shown in FIG.
The pitch synchronization signal PS1 becomes “1” when the pitch is 9.
(In this case, this signal “1” is a
This is the pitch synchronization signal of channel 1), and this is the shift
It is circularly held in the register 53 and is stored in the time slot 2.
5, when the timing signal φFS1 (25) is generated,
It is latched to the tsuchi circuit 55 and corresponds to channel 1.
The filter operation request signal φF1 to be
It rises to "1" at step 25. This signal φF
1 is total up to time slot 24 of next cycle
The signal “1” is maintained for a time width of 64 time slots.
hold <Timing signal generation circuit 39: Fig. 13> In FIG. 13, the timing signal generation circuit 3
9 is the decoder 56 and the counter 57 described above.
is given from input interface 38 in FIG.
Filter operation request signal φF for each channel
1 to φF8 to control the filter calculation operation.
Arithmetic timing generation circuit that generates timing signals
391-398 for each channel (Ch1-Ch8)
It is equipped with. In the figure, channel 1 circuit 391
The details were shown only for episodes 2 to 8 of other channels.
Roads 392 to 398 also have the same configuration, and if you enter there
The input timing signals T(33), T(49),...
Only the time relationship is different. timing signal T (33),
T(49), . . . are generated from the decoder 56. Before
Similar to the above, in the code indicating the timing signal,
The numbers in brackets represent one calculation cycle (shown in Figure 3).
64 time slots)
and the time corresponding to that time slot number.
The timing signal becomes “1” in the slot.
to show that Other signals generated from decoder 56
The same goes for the timing signal;
Its timing signal by referring to the numbers in
In which time slot occurs (“1”
) can be easily determined. For example, timing signal
No. T (33) has a time slot as shown in Figure 17.
The signal becomes “1” at port 33, and is reliable.
No. T (3-18) is from time slot 3 to 18.
The signal becomes "1" between the two. Channel 1 calculation timing signal generation circuit 3
To explain 91, the filter calculation request signal
φF1 and timing signal T (33) are connected to AND circuit 59
given to. Therefore, perform filter operation
If required, time slot 3
At the timing of 3, the output of the AND circuit 59 becomes “1”
becomes. The output signal of this AND circuit 59 and this
The signal was delayed by one time slot using the delay circuit 60.
The signal is applied to the OR circuit 61. This or time
The output of line 61 is the filter data sampling clock.
Digital filter circuit as the check signal RLA1
It is used to control the unit delay in
This signal RLA1 is timed as shown in Figure 17.
When the slots are 33 and 34, it becomes "1". The AND circuit 62 is connected to the output of the AND circuit 59 and the output of the AND circuit 59.
Even-odd identification data EOA1 of Yannel 1 (this is the
Output from the parameter supply circuit 48 in Figure 11
) is inverted by the inverter 63, and the signal is
Given. We are trying to realize this data EOA1
When the order of the filter characteristic is an even number, the signal
The signal is "1", and the signal is "0" when the order is an odd number.
The output of the AND circuit 62 is sent to the delay circuit 64 for 2 times.
The slot is delayed and the inhibit signal INHA1 and
is output. When the filter order is odd,
The output signal of the code circuit 62 is sent to the time slot 33.
becomes “1” and the time after that 2 time slots
When slot 35, signal INHA1 becomes “1”
(See Figure 17). If the filter order is even, the
The number INHA1 is always “0”. This invitation
Signal INHA1 is used for calculation of digital filter circuit.
In operation, the highest even order (32nd order) operation is performed.
Odd-order filter characteristics are achieved by inhibiting
used to. Timing signals T(3-18) and T(35-50) are on.
It is input to the circuit 65, and its output and AND
The output of the circuit 59 is input to the OR circuit 66.
Ru. The output of the OR circuit 66 is connected to one tie in the delay circuit 67.
mslot delayed first shift clock signal
It is output as φFFA1 (see FIG. 17). Ma
In addition, the output of the OR circuit 66 and the output of the delay circuit 64 are
The signal inverted by the inverter 68 is sent to the AND circuit 69.
, and its output is connected to the delay circuit 70 to
The imslot-delayed signal is used as the second shift clock.
It is output as a signal φFLA1 (see FIG. 17).
Signal φFLA1 is a tie if the filter order is even.
It is “1” when the number is 36, but if it is an odd number
In this case, it is “0”. These shift clock signals
φFFA1 and φFLA1 are digital filter circuits
In order to perform calculation operations for each order in a time-sharing manner,
In order to
The musical tone signal sample value data corresponding to the delay stage is
Used for next shift. Times according to timing signal T(35-50)
A multiplication tie that is “1” between 35 and 50.
The timing signal PDOA1 (see Figure 17) is
Musical tone signal sample value in digital filter circuit
The period during which the data should be multiplied by the filter coefficient
It gives instructions. Corresponding to other channels 2 to 4 in A series
to the calculation timing signal generation circuits 392 to 394.
Timing signals T(49) and T(19) used in
-34), T (51-2), ... are ties for channel 1.
timing signals T(33), T(3-18), T(35-50)
The timing was shifted by 16 time slots.
It is something. Therefore, the circuit 391 of channel 1
Same as each signal RLA1~PDOA1 output from
Signals RLA2~PDOA2,...RLA4~PDOA
4 is the circuit 392-394 of other channels 2-4
The timings are shifted by 16 time slots from
This occurs during Based on this, the A series day
Digital filter circuits (especially multipliers and
In the data section 41), one operation cycle = 64 tie
Time interval every 16 time slots between slots
to perform filter calculation operations for four channels 1 to 4.
It is now possible to have it done in a time-divided manner.
Ru. Arithmetic data corresponding to each channel 5 to 8 of B series
Also in the timing signal generation circuits 395 to 398
16 time slots shifted between each channel
Timing signals T(49) and T(19
-34), T(51-2), ... are used, and the same as above.
various signals RLB1~PDOB1,...RLB4~
PDOB4 is generated. Arithmetic timing signal generation circuit corresponding to A series
Each signal RLA1~ generated in 391~394
PDOA4 is given to the A series state memory 40.
and is emitted by circuits 395 to 398 corresponding to the B series.
Each of the generated signals RLB1 to PDOB4 is a B-series stream.
The data is applied to the state memory 42 (FIG. 11). <State memory 40: Fig. 14> In FIG. 14, the A-series state memory 4
0 is the step corresponding to each channel 1 to 4 of the A series.
It is equipped with root memories 401 to 404 in parallel.
Ru. Only the state memory 401 of channel 1 is detailed.
Although the details are shown, the states of other channels 2 to 4
The memories 402 to 404 also have the same configuration, and there
The input signals are different. Each of the above
Calculation timing signal generation times corresponding to channels 1 to 4
Each line generated from paths 391 to 394 (Fig. 13)
Signal RLA1~PDOA1,...RLA4~PDOA4
is the state memory corresponding to the channel of self
401 to 404, respectively. The state memory 40, multiplier and
Before explaining the details of the accumulator section 41, this
The basis of a digital filter circuit consisting of these circuits is
Schematic diagrams shown in Figures 18 and 19 regarding this operation
Explain with reference to. <Basic operation of even-order filter calculation: Figure 18> Figure 18 shows the above digital filter circuit.
Realizes filter characteristics consisting of an even number order (32nd order).
Explains the basic operation of FIR type filter operation when
A is a block diagram, b is a schematic diagram for each
Shift register SR of a at calculation timing
1. Each stage of SR2 Q0~Q15,Q16~
It shows the state of the musical tone signal sample value in Q31. The first shift register SR1 has 16 stages.
First, the digital musical tone signal signal to be filtered.
sample value data x_ois input via selector SEL1
be done. New sample via selector SEL1
value data x_oAs a signal to capture the
Filter data sampling clock signal RLA
(RLA1 for channel 1) is used and
As shift clock pulse of shift register SR1
The above-mentioned first shift clock signal φFFA (ch.
For channel 1, φFFA1) is used. 1st
Each stage Q0 to Q1 of shift register SR1
5 contains 16 samples from sample point n to n-15.
pull value data x_o~x_o-15is retained. This schiff
The output of the final stage of register SR1 is selected.
Sampling clock signal via data SEL1
When there is no RLA, it returns to the first stage. this
Shift register SR1 is shifted only to the right.
Ru. The second shift register SR2 also has 16 stages.
Then, the output of the first shift register SR1 is selected.
It is input via data SEL2. Selector SEL2
A signal to take the output of SR1 into SR2 via
As mentioned above, the filter data sampling method is
clock signal RLA is used to control the shift clock of the SR2.
The clock pulse is the second shift clock signal mentioned above.
φFLA (φFLA1 for channel 1) is used
be done. Each step of this second shift register SR2
The stages Q16 to Q31 have sample points n to n-.
16 sample value data from 16 to n-31
x_o-16~x_o-31is retained. Shift register SR2
The final stage Q31 of is passed through selector SEL2.
When there is no sampling clock signal RLA, the first
Connected to stage Q16. This shift register
The SR2 is a bidirectional shift type, and the sampling
Right shift mode when clock signal RLA is “1”
When it is “0”, it becomes the left shift mode. Stage Q15 of shift registers SR1 and SR2
and the output of Q16 are added by adder ADD, and the output of
The addition result is given to the multiplier MUL and filtered
The number COEA is multiplied. The multiplication result is Akiyum
The multiplication result with respect to all orders is given to the
The fruits are accumulated there. In this way, a
The data for one sample point is output from the storage unit ACC.
The router calculation result is output. Adder ADD adds sample value data for two sample points.
and add the common filter coefficient COEA to it
The reason for multiplying by the multiplier MUL is based on the above-mentioned
Due to the symmetry of the router coefficients. That is, the symmetrical relationship
The two sample value data in
Multiply them separately because they are multiplied by the router coefficients
Both samples are added together and then multiplied once without
Multiply the pull value data by coefficient at the same time.
ing. In Figure 18b, the calculation timing of the vertical axis
Each time slot corresponds to the master clock.
Proceed to. The numbers shown therein are in the order of convenience.
1 calculation cycle (64 time slots) as shown
This is not an absolute indication of the time slot number in the
do not have. In the example in the figure, at calculation timing 1, the system
Each stage Q0 to Q of foot registers SR1 and SR2
x to 31_ofrom x_o-31Sampling of up to 32 sample points
Contains value data. In the example in the figure, the sample is
Assume that the operating clock signal RLA becomes “1”.
ing. This allows the shift clock signal to
According to φFFA and φFLA, shift register SR1,
SR2 is shifted to the right by one stage, and this calculation timer is
In timing 2, the state is as shown in the figure. At this time
The shift clock signals φFFA and φFLA are channel
In case of 1, the columns of φFFA1 and φFLA1 in Figure 17
This occurs at time slot 34 as shown in
be. As is clear from the figure, the next time period
The rotor generates shift clock signals φFFA and φFLA.
Therefore, at calculation timing 3 in Figure 18b,
The states of each stage Q0 to Q31 do not change.
However, 16 times from calculation timing 3 to 18
The slot width is the multiplication time for channel 1.
timing signal PDOA1 (Fig. 17) is generated.
It corresponds to Muslot 35-50, and between this
Multiplication and accumulation are performed. In other words, at calculation timing 3, stage Q1
x in 5 and Q16_o-14and x_o-15sample of
The value data is added by the adder ADD, and the first
The 6th order filter coefficient is multiplied and the result is
Retained in Umuleta ACC. Calculation timing 4 to 18 is 1 time
For each slot, the first shift register SR1 is
shift, the second shift register SR2 shifts left
The status of each stage Q0 to Q31 is as shown in the figure.
The sea urchins change sequentially. Therefore, at calculation timing 4
is x_o-13and x_o-16is added to this, and the 15th order
The ultur coefficients are multiplied and the result is the accumulator
Accumulated in ACC. At the next calculation timing 5
x_o-12and x_o-17A similar operation is performed for
Regarding the two sample value data at symmetrical positions,
Similar filter coefficient calculations are performed sequentially on a time-sharing basis,
At calculation timing 18, x is at the last symmetrical position_o+1
and x_o-30A similar operation is performed on
The order filter operation is completed. Next calculation time
At ng 19, another shift is made, as shown.
In order of time delayed to each stage Q0 to Q31
For each sample value data x_o+1~x_o-30are lined up. <Basic operation of odd-order filter calculation: Figure 19> Figure 19 shows a filter consisting of an odd order (31st order).
Basics of FIR type filter operation when realizing characteristics
This is a schematic diagram for explaining the operation, and a is a block.
In the figure, b is the shift rate of a at each calculation timing.
Each stage Q0 to Q15 of registers SR1 and SR2,
Indicates the status of musical tone signal sample values from Q16 to Q30.
vinegar. Each block in a is as shown in Figure 18a.
The difference is that stage Q16
The output is given to adder ADD via gator GT
Is Rukoto. Gate GT is an inhibit signal
Invert INHA (INHA1 for the first channel)
It is now controlled by the corresponding signal.
Output of stage Q16 when signal INHA is “1”
Prohibits signals from being applied to adder ADD.
Also, the 16th stage of the second shift register SR2
The 15th stage Q30 and the 1st stage are not used.
Stage Q16 is connected via selector SEL2.
It will be done. In b, the state of the first shift register SR1
The changes are the same as in Figure 18b. 2nd shift register
The state change of star SR2 is shown in Figure 18 (even number order case).
It is slightly different. of the second shift register SR2
The shift clock signal φFLA is calculated at calculation timing 4.
In the even-order mode, it is “1”, but in the odd-order mode
mode, it will be “0” (for channel 1, it will be “0”).
See time slot 36 in the φFLA1 column in Figure 17.
(see). Therefore, in the odd-order mode, as shown in Fig. 19b,
The contents of the second shift register SR2 as shown
is not shifted at calculation timing 4, and is not shifted at calculation timing 4.
It is sequentially shifted to the left between timings 5 and 19. At calculation timing 3, shift register SR1,
Each stage Q0 to Q30 of SR2 has 31st order delays.
Musical tone signal sample value x corresponding to the delay stage_o+1~
x_o-29is in order and is in stage Q15.
sample value x of center order_o-14Contains. 6th
As shown in the figure, the symmetry of the odd mode is
For the order located in the center, it is unique
filter coefficients are assigned. Therefore, the operation
At timing 3, the inhibit signal INHA is activated.
Therefore, the output of stage Q16 is inhibited, and the central order is
Only the output signal of the corresponding stage Q15 is added to the adder.
In addition to ADD, the central order is
Multiply by the corresponding unique filter coefficient. At calculation timing 4, the first shift register
Only SR1 is shifted right and the second shift register
Data SR2 is not shifted. Therefore, stage Q
x for 15_o-13enters, and x in Q16_o-15is included
There is. In addition, the inhibit signal INHA is “0”.
Then, Gate GT opens. Thus, the central order
sample value x corresponding to the order on both sides of the number_o-13,
x_o-15is given to the adder ADD and added, and multiplied by
In the filter MUL, both are multiplied by a common filter coefficient.
calculated. At calculation timings 5 to 18, SR1 shifts to the right in sequence.
SR2 and SR2 are sequentially shifted to the left, as shown in the figure.
The sample value at the position is the stage Q15, Q1.
6, both are added and a common filter coefficient is obtained.
is multiplied. <Digital filter circuit: Fig. 14> Referring to Figure 14, the screen corresponding to channel 1
The state memory 401 will be explained. 16 stays
The one-way shift register 71 shown in FIG.
The one corresponding to the first shift register SR1 in Figure 9
and the first shift corresponding to channel 1
The shift is controlled by the clock signal φFFA1.
Ru. Supplied from tone generator 18 (Figure 2)
digital musical tone signal sample value data
TDX is input to the latch circuit 73, and the latch
channel 1 signal according to the XLDA1 signal.
The sample value data is taken into the latch circuit 73.
Ru. Each of the musical tone signal sample value data TDX
Channel time division timing (see Figure 3)
corresponding to each channel 1 to 8.
Timing signal XLDA1~XLDA4, XLDB1~
XLDB4 is generated from decoder 56 (Figure 13)
be done. As mentioned above, each signal display in Figure 13
The number in parentheses at the end is the timer at which the signal occurs.
Indicates the muslot number. Corresponds to each channel
A latch similar to the latch circuit 73 is included in the state memory.
There are two circuits, each with a corresponding one.
Timing signal XLDA1 to XLDA4, XLDB
1 to XLDB4 for each channel 1 to 8.
The sound signal sample value data TDX is latched separately.
and is thus demultiplexed. Channel 1 latched in latch circuit 73
The musical tone signal sample value data is input to the A input of the selector 74.
Gives strength. The selector 74 operates as shown in FIG.
is given from the calculation timing signal generation circuit 391.
Filter data sampling clock signal RLA
When 1 is “1”, A input is selected, and other
is the 16th shift register 71 that is added to the B input.
Select the stage output signal. As mentioned above, this
The signal RLA1 is synchronized with the pitch of the musical tone.
and select a new sample using selector 74 in synchronization with the pitch.
Select pull value data (A input) and shift it
It is given to register 71. It is clear from Figure 17.
Time slot where signal RLA1 becomes “1”
At step 34, shift clock signal φFFA1 becomes “1”.
Therefore, the shift register 71 is connected to the selector 74.
The new sample value data given from
Take in the stage (Q0). Next time slot 3
5, the shift operation is temporarily stopped and the following time slot is started.
As mentioned above, the steps 36 to 51 are sequentially shifted to the right.
It is. The bidirectional shift register 72 is shown in FIGS.
Corresponding to the second shift register SR2 in the diagram
It is. Each step of this bidirectional shift register 72
Pages Q16 to Q31 are selected by selector SL as shown.
Consists of 1 to SL16 and latch circuits LC1 to LC16.
connected for bidirectional shifting.
ing. In other words, the selection of the first stage Q16
The first shift register 7 is connected to the A input of the vector SL1.
The output signal of the final stage (Q15) of 1 is input.
and selectors for each of the other stages Q17 to Q31.
The A inputs of SL2 to SL16 are connected to the previous stage.
The outputs of latch circuits LC1 to LC15 are input. Ma
In addition, the B input of selectors SL1 to SL16 of each stage
For power, the next stage latch circuit LC2~LC1
6.The output of LC1 is input. This allows each
When the A input of selectors SL1 to SL16 is selected
When the right shift mode is selected and the B input is selected,
and enters left shift mode. Each selector SL1~SL
Sampling clock signal as selection signal of 16
When RLA1 is used and this is “1”, the A input
Select, that is, shift to the right mode. However, odd numbers
To disable stage Q31 in the next mode.
For this reason, selector SL15 of stage Q30 is different from others.
are somewhat different. That is, this selector SL
15 is provided with a C input, and the stage
The output signal of Q16 is added. Regarding channel 1
Even/odd identification data EOA1 is “1” (that is, even number
(next mode), the AND circuit 751 is enabled.
When the signal RLA1 is “0”, the AND circuit 7
The output of 51 becomes the signal “1”, which causes the select
Kuta SL15 selects B input and stage Q31
is given to stage Q30 (left shift
). When EOA1 is “0” (odd order mode)
) when the AND circuit 761 is enabled and the signal
When RLA1 is “0”, selector SL15 inputs C
is selected, and the output of stage Q16 becomes stage Q3.
0 (jumps Q31 and shifts left)
). With the above configuration, the first and second shift registers
The changing state of the contents of stars 71 and 72 is in even order mode.
Figures 18b and 19 depending on the odd mode and
It will be exactly the same as shown in Figure b. First stage Q1 of second shift register 72
The output signal of 6 is sent to gate 76 via gate 75.
Given. Gate 75 is an inhibit signal
Controlled by the inverted signal of INHA1
This corresponds to gate GT in Figure 19.
Ru. The gate 76 is connected to the first shift register 71.
Output signal (output signal of stage Q15) and gate
A second shift register 7 provided via 75
Input the output signal of stage 2 (output signal of stage Q16).
and multiply timing signal PDOA1 (Fig. 17).
(see). The output of gate 76 is a multiplier and an accumulation rate.
section 41 to an adder 77, where the two
The sound signal sample value data is added. This addition
The adder 77 corresponds to the adder ADD in FIGS. 18 and 19.
It corresponds to the above. The output of adder 77 is a delay circuit
78 and is delayed by one time slot to the multiplier 79.
is input. Multiplier 79 via delay circuit 78
A delay circuit is applied to the given musical tone signal sample value data.
Filter coefficient data given via 80
It is multiplied by COEA. Output of multiplier 79
is delayed by four time slots in the delay circuit 81 and the
provided to the lid 82. Shift control of shifter 82
The input is a delay that sets a delay of 5 time slots.
Weighting data WEIA is given via circuit 83.
It will be done. This multiplier 79 and shifter 82
This corresponds to the multiplier MUL in Fig. 19.
Ru. In other words, as mentioned above, the filter coefficient data
COEA is the effective bit data of the filter coefficient.
The multiplier 79 calculates the effective value of this filter coefficient.
The bits are multiplied by the musical tone signal sample value data.
be exposed. Then, this multiplication result is sent to the shifter 82.
The number of bits according to the value of the weighting data WEIA
The real number of filter coefficients by shifting by
When the multiplication of and the musical tone signal sample value data is completed,
Ru. The output of the shifter 82 is fed to the accumulator 84.
and the multiplication result corresponding to each order for one channel.
The fruits are accumulated. Accumulator 84
The output of is input to the latch circuit 85, and the operation end terminal
It is latched according to the timing signal FENDA. child
The signal FENDA is generated from the decoder 56 in FIG.
be born. As shown in the figure, this
Signal FENDA is time slot 8, 24, 40,
It becomes "1" at 56. time slot 56
Then latch the calculation result of channel 1, and in 8
Latch the calculation result of channel 2, and
Latch the calculation result of channel 3, and at channel 40
Latch the calculation result of channel 4. Decoder 56
From is the B series calculation end timing signal FENDB
is generated in the same way. The multiplier and accumulation unit 41 has four channels.
It is shared in time division by Yannel. That is,
Adder 77 includes state memory for channel 1.
Not only the output of gate 76 of 401 but also the channel
The settings in the state memories 402 to 404 of the modules 2 to 4
The output signal of a gate with similar function is
are input multiple times. Each state memory 401
The output gate 76 of ~404 has 16 time slots.
multiplication timing signals PDOA1 to PDOA4
is shifted by 16 time slots at different timings.
are input respectively. Therefore, the adder 77 has
The signals of channels 1 to 4 are displayed every 16 time slots.
The input is divided and multiplexed. Filter coefficient data
COEA and weighting data WEIA are divided into four channels.
16 times with the same timing as above.
Each slot is time-division multiplexed, and one channel
1 in 16 time slots regarding Yannel.
The data from the next to the 16th order are time-division multiplexed.
Ru. B-series state memory 42, multiplier and
The humulator section 43 also has the same configuration as in FIG.
However, the timing of various signals may vary accordingly.
There is. A series and B series as shown in Fig. 14.
Digital filter circuit (i.e. state memo)
40, 42, multiplier and accumulator section 4
Regarding each channel 1 to 8 in 1, 43)
FIG. 20 shows the timing of filter operation. No.
In Figure 20, the shift 1 column shows the first shift.
Shifter register (71 for channel 1)
The shift 2 column shows the timing of the second shift.
Shifter register (72 for channel 1)
It shows the timing. The direction of the arrow is the shift direction
(right shift or left shift). Each chia
The channel shift timing is the calculation timing signal.
Generated from generation circuits 391 to 398 (Fig. 13)
The first and second shift clock signals φFFA1
~ φFFB4, φFLA1 ~ φFLB4 generation timing
It is compatible with A filter function is used for shift operation.
Shift operation and memory data refresh for calculation
There is a dummy shift operation for For example,
For channel 1, the system in time slots 4 to 19
The shift is a dummy shift. In the shift 2 column
The (←) symbol indicates a left shift in even mode.
and do not shift when in odd mode.
shows. In Figure 20, the INH column is the inhibit
Indicates the generation timing of signals INHA1 to INHB4.
ing. When in odd-numbered mode, the time slot is marked with ○.
Inhibit signal INHA1 to INHB
4 becomes "1". The PDO column is for each channel.
Multipliers and
Musical tone signal sample value data is input to the humulator sections 41 and 43.
Indicates when data is input. this
is the multiplication timing signal PDOA1 of each channel
~ Corresponds to the timing of PDOB4 occurrence.
The SUM column is the output time of the accumulator 84.
It shows the PDO and SUM timing
There is a delay of 6 time slots in between.
5 time slot delay due to routes 78 and 81 and
1 time slot delay due to cumulative rate 84
by. The output timing of the accumulator 84
At the last time slot, the computation end timing signal is sent.
No. FENDA occurs and the output of accumulator 84
is taken into the latch circuit 85. <Parameter memory 47: Fig. 21> FIG. 21 shows the memory format of the parameter memory 47.
Shows an example of a matte key group table
table, touch group table, parameter address
It consists of a stable and a parameter bank.
Actual filter parameters are in the parameter bank
is stored in the parameter address table.
is the parameter to be read from the parameter bank
address data is stored. key glue
A table groups keys according to each key.
remembers information to be used. As an example, the number of keys is 88,
The number of groups is 44 and in the key group table
indicates that the key belongs to the address position corresponding to each key.
Relative address data about key groups (key
group address). obey
The key group table is set according to the key code KC.
address. This key group table
is a predetermined absolute address of the parameter memory 47
(referred to as offset address OADS)
Occupies memory area. The tatsuchi group table is a key tatsuchi for each tone.
Group the touch intensity corresponding to each level of intensity.
It remembers the information to be converted into a file. As an example, the number of tones
is 32, and this Tatsuchi group table has a tone of
32 tone-specific areas corresponding to code VN values 0 to 31
It also includes a touch cord TCH.
As an example, there are 64 levels of touch strength that can be expressed as
Yes, each tone area corresponds to Tatsuchi 0 to 63.
It has 64 address locations. Each touch strong
The address position corresponding to the touch intensity is
Relative address data regarding the Tatsuchi group to which it belongs
(referred to as Tatsuchi group address) is memorized.
ing. As an example, the number of touch groups is 16.
Ru. Therefore, the Tatsuchi group table
Addressed by code VN and touch code TCH
It will be done. This touch group table is a parameter
A predetermined absolute address of the memory 47 (this is offset)
The memory address starting from address OAD1)
It occupies the rear. This tatsuchi group table
The absolute address data for reading is 6 bits.
5-bit tone above the touch code TCH
Combined with code VN to create 11-bit relative address data.
data (with offset address OAD1 set to 0)
address) and use this as the offset address
Created by adding to OAD1. A parameter address table is provided for each key group.
for each touch group for each group and for each tone.
address that stores the corresponding filter parameters.
relative address data (parameter address and
). This parameter address
The table has 44 keys corresponding to each key group 0-43.
This key group area contains
Is the group area the key group table mentioned above?
Add by key group address read from
will be responded to. Each key group area has tones 0 to 31
Contains 32 tone-specific areas corresponding to the
This tone area is divided by tone code VN.
addressed. Each tone area is Tatsuchiguru.
It has 16 address locations corresponding to numbers 0 to 15.
and each address position corresponds to the touch group text described above.
to the touch group address read from the cable.
It is then addressed. In addition, at the 1 address position
A 2-byte storage location has been allocated and
The above parameter address data is written in 12 bits.
It is remembered. This parameter address table
is a predetermined absolute address of the parameter memory 47
(This is called offset address OAD2)
Occupies the memory area that begins. This parameter
Absolute address for reading address table
The data has the lowest 1 bit as “0” or “1”
(This means that one address position is 2 bytes or
occupies 2 absolute addresses), and 4 above it.
Locate the bit touch group address data.
and then add a 5-bit tone code VN above it.
position, and then add a 6-bit key glue above it.
A total of 16 bits of relative address
data (set offset address OAD2 to 0)
address) and set it as an offset address.
is created by adding it to OAD2. For example, the parameter bank has 2620 types of filters.
The router parameters are memorized and the parameter
2620 parameters corresponding to responses 0 to 2619
Contains a memory area. One parameter memory
rear is a 32-byte storage location (32 absolute addresses)
position), and one set of filters for 16 orders.
Stores parameters corresponding to coefficients. primary
Several minutes of filter coefficients are stored in 2-byte storage locations.
The breakdown is, as mentioned above, 12-bit
filter coefficient data (COE) and 3-bit weight
The finding data (WEI) and the 1-bit even/odd identification data
consists of data (EO). However, weighted data
(WEI) and odd-even identification data (EO) are one set of parameters.
In the data, the first order is common to each order.
Store only in the storage location of , and store in the storage location of other orders
I don't remember. However, weighted data (WEI)
can be stored independently for each order.
It is Noh. This parameter bank contains the parameters described above.
parameters read from the data address table.
address by the data address. parameters
The bank is a predetermined absolute address in the parameter memory 47.
address (this is called offset address OAD3)
Occupies the memory area starting from. This parameter
Absolute address data for reading data bank
converts 12-bit parameter address data to 17-bit
Relative address data (offset address)
The upper 12 bits of the address (with OAD3 set to 0)
Create the relative address data by positioning
and add this to offset address OAD3
It is created by This absolute address
The lower 5 bits of the data are changed sequentially in 32 steps.
specified by the parameter address by
From the 16th order in the 1-parameter storage area
A set of filter parameters are read out sequentially.
Ru. Hierarchical parameters as shown in Figure 21
The data memory structure can save memory capacity.
It is advantageous because it can be done. 44 keys without doing it like this
A combination of groups, 32 tones, and 16 touch groups.
Individual filter for all (22528 ways)
Assuming you memorize the parameters, 22528 x 32 bytes
However, as shown in Figure 21,
Then 1408 (=44) in the parameter address table
×32) ×32 bytes and parameter bank 2620 × 32
The storage capacity is only 4028 x 32 bytes including bytes.
Not required. In other words, key groups, tones,
Even if the combination of Tutsi groups is different, the filter
Common parameters may be used
Therefore, in the example in Figure 21, there are 22528 combinations.
As a structure that shares 2620 types of parameters.
This saves memory capacity. <Parameter processing unit 45, parameter
parameter selector 46, parameter memory 47,
Meter supply circuit 48, 49: Fig. 15> The parameter processing unit 45 is
For the static mode of
Controls reading of parameter memory 47
It is. The program memory 451 includes the above-mentioned
Execute read control of parameter memory 47
The program to do this is stored in memory. Program card
Counter 452 reads program memory 451
Generate program step signal PC for
8-stage shift register 86 and addition
device 87, gates 88, 89, end detection circuit 90
It includes counting operation for 8 channels.
Do it in a time-divided manner. Key-on pulse KONP is in
It is inverted by the inverter 91 and sent to the control input of the gate 88.
join. This key-on pulse KONP
The signal becomes “1” at the beginning of each channel.
are time-division multiplexed. addition
A gate circuit 87 applies a gate to the output of the shift register 86.
This is to add “1” given from 89.
The addition result is transferred to the shift register via gate 88.
data 86. The end detection circuit 90 shifts
The value of the output of the register 86 is the final step of the program.
This is to detect whether the step has reached the final step.
If the step is not reached, the signal “0” is output and the
The signal “1” is passed through the inverter 92 to the gate 89.
A signal that is applied to the control input and instructs the count up by 1.
The signal “1” is given to the adder 87.
However, when the final step is reached, the signal “1” is set.
output and gate the signal “0” through the inverter 92.
gate 89, close the gate 89, and count.
prevent this from happening. With the above configuration, the program counter 452
The content of the step signal PC is the key-on pulse.
It is reset to “0” when a KONP occurs.
After that, every time the shift register 86 goes around (8 times)
(for each muslot), the count will be increased by 1, and eventually
Counting stops when the final step is reached.
Ru. As an example, the number of program steps is 37.
The step signal output from the counter 452
PC sequentially from "0" to "36" (final step)
Change. Step signal PC is shift register 8
6 outputs, and 8 channels are time division multiplexed.
It is exacerbated. The program memory 451 stores input steps.
Select control signal SELC according to the step of signal PC
Read 1 to SELC4 and set the offset address.
Address data for reading the memory 453
Read out. The offset address memory 453 is
Values of the offset addresses OADS to OAD3 mentioned above
I remember. Offset address memory 45
Offset address data read from 3
ADOF (any of OADS to OAD3) is adder 4
54. Adder 454 is selector 45
Relative address data RADD given from 5 and
Add the offset address data ADOF,
Parameterize the output as address data PRAD.
It is added to the address input of data memory 47. Key group address register 456, touch
Group address register 457, parameter address
Each dress register 458 has eight stages of shifting.
Consists of registers, key group address data
KEYG, Tatsuchi Group address data TCHG,
Parameter address data PAD for each channel
The information is stored in a time-division manner. Each register
Selectors 93-95 are on the input side of 456-458.
read from the parameter memory 47.
The output data is added to one input of each selector.
Ru. The other input of each selector 93 to 95 is
The outputs of registers 456-458 are added. selector
The selection control signals SELC2 to SELC4 of 93 to 95 are
from the program memory 451.
The parameters are set according to the steps of the program.
Register read output data of meter memory 47
data 456 to 458 or register
Circulate the data once imported into the data
Controls whether to hold or not. As is clear, para
The key group address mentioned above from the meter memory 47
Set this to the key group when the data is read.
The address register 456 is loaded with the above-mentioned tag.
When the group address data is read
This is stored in the touch group address register 457.
The above parameter address data is read.
When issued, set this to the parameter address register
Select control signal SELC2~
SELC4 is generated. Addresses stored in each register 456 to 458
Selector 4 for response data KEYG, TCHG, PAD
55. The key code is in sector 455.
KC, tone code VN and touch code TCH
is the step output from the program counter 452.
The least significant bit of the drop signal PC, PCLSB, and this step
“4” (binary “100”) was subtracted from the Tsupu signal PC.
Data PC-4 is also input. selector 45
5, the selection given from the program memory 451.
The input data is set to the specified value according to the selection control signal SELC1.
Select a combination and set the selected data to a relative address.
corresponds to a predetermined weight in the data RADD
bit position and thus the relative address data.
Create and output data RADD. This parameter processing unit 45
The contents of the 37 steps executed are as follows.
It is. When PC=0: Read key group table
process Key code KC is set by selection control signal SELC1.
Select and set the offset address data as ADOF.
offset address of key group table
Read OADS. In addition, selection control signal SELC2
key the output data of parameter memory 47.
Load into group address register 456. child
As a result, the key group of the parameter memory 47
Keygle corresponding to key code KC from table
The loop address is read and this is stored in register 45.
6 is stored. When PC=1: Read touch group table
processing Tone code VN and Tatsuchiko by signal SELC1
Select the code TCH and set the TCH to the least significant bit.
Position the VN above the relative address data
Create RADD. Offset address data
Offset of Tatsuchi group table as ADOF
Reads the address OAD1. Also, the signal
The output data of parameter memory 47 is set by SELC3.
the touch group address register 457.
Get into it. As a result, the data in the parameter memory 47 is
Tone code VN and tag from the Tsuchi group table.
Tatsuchi group ad compatible with Tatsuchi code TCH
The response is read out and stored in register 457.
is applied. When PC=2, 3: Parameter address table
Bull read processing Key group address data is set by signal SELC1.
Ta KEYG, Tone Code VN, Tatsuchi Group Ad
response data TCHG, lowest bit of step signal PC
Select PCLSB, starting from the least significant bit.
Position in the order of PCLSB, TCHG, VN, KEYG
Create relative address data RADD. day
Parameter address table as ADOF
Read offset address OAD2. Also,
Output of parameter memory 47 by signal SELC4
data to parameter address register 458.
Get into it. As a result, the parameters of the parameter memory 47 are
appropriate parameters from the parameter address table.
The address is read and placed in register 458.
Stored. As mentioned above, one parameter
Address data consists of 12 bits and is recorded in 2 bytes.
It is stored in the storage location (see FIG. 21). bits
When PCLB is “0” (step PC=2),
The lower 8 bits of parameter address data are read.
is issued and PCLSB is “1” (PC=3 step).
), its upper 4 bits parameter address
Data is read. In selector 95, this
Parameter address data is arranged as 12-bit data.
Sort the bit positions so that they are columnar and register them.
458. When PC=4 to 35: Read parameter bank
process Parameter address data by signal SELC1
Select step signal PC-4 subtracted by 4 from PAD
Then, the positions are placed in the order of PC-4 and PAD from the least significant bit.
to create relative address data RADD.
In addition, the parameter bank can be used as a data ADOF.
Read offset address OAD3. signal pc
-4 is that in 32 steps from PC=4 to 35.
The value changes from "0" to "31". Therefore, Pa
32 bytes specified by parameter address
A set of filter parameters (see Figure 21)
) is the parameter bank of parameter memory 47.
One byte at a time is read out sequentially. When PC=36: Program counter 452
Stop and read filter parameters
End the Kens. File read from parameter memory 47
The data parameters are input to the timing synchronization circuit 459.
Powered. This circuit 459 is a program step
Decoding of signal PC and timing signal generation circuit 39
The timing signal provided by the driver 56 (FIG. 13)
signal group TS1, and based on these signals, each
Order filter parameters at specified timing
Synchronize and output. The output of this synchronization circuit 459
force is a filter parameter for static mode
To A input of parameter selector 46 as SPR
Given. To B input of parameter selector 46
is from the microcomputer interface 44 (Figure 11).
Output filter parameters for dynamic mode
The meter DPR is given. Selection of selector 46
Is there a microcomputer interface 44 for the control input SB?
The dynamic/static selection signal output from
No. DS is given, and when in dynamic mode, enter B.
Select the force parameter dpr and stats spider
When loading, select the A input parameter SPR. The output of the selector 46 is the parameter of each series A and B.
data supply circuits 48 and 49. A series episode
A detailed example of only the circuit 48 is shown, but the B series circuit 49
also have the same configuration. to the parameter supply circuit 49.
The distribution circuit 485 receives serial data from the selector 46.
A series of parameter data given to Al
Import data regarding channels 1 to 4 of
In addition to parallelizing this for each channel,
router coefficient data (COEA1 for channel 1),
Weighting data (WEIA1 for channel 1),
Even-odd identification data (EOA1 for channel 1)
Parallelize them separately and correspond to each channel
It is distributed to memory circuits 481-484. like this
For distribution control, appropriate timing signal TS2
is the decoder 56 of the timing signal generation circuit 39
(FIG. 13) and applied to the distribution circuit 485.
available. Memory circuits 481 to 484 are for channel 1.
A detailed example is shown below, but the same applies to other channels.
It's like that. 12-bit filter coefficient data COEA
1 is a 16-stage shift lever via selector 96.
It is input to the register 97. This filter coefficient data
The data COEA1 corresponds to 16 orders in 16 time slots.
data is time-division multiplexed, and this 16-order
data is stored in each stage of the shift register 97.
It is captured. The contents of shift register 97 are selected.
It is circulated and held through the tank 96. 3 bit weight
The finding data WEIA1 is input to the latch circuit 98.
It will be done. The 1-bit even-odd identification data EOA1 is easy.
input to the circuit 99. selector 96 and rat
The circuits 98 and 99 are controlled by appropriate controls (not shown).
This is done at the appropriate timing according to the control signal. vinegar
In other words, when in static mode, key presses
Read from parameter memory 47 in response to the beginning
The parameter data for the 16th order
synchronization circuit 459, selector 46, distribution circuit 4
85 to the memory circuit 481.
In synchronization with the timing, the selector 96 selects 16 orders of frames.
Shift register 97 to filter coefficient data COEA1
The latch circuits 98 and 99 load the weighting data into
Latch data WEIA1 and even/odd identification data EOA1.
do. From then on, a new push will be applied to that channel.
Until the key is assigned, the shift register 97,
The memories of the switch circuits 98 and 99 are retained. on the other hand,
When in dynamic mode, the microcontroller interface
Ace 44 (Figure 11) to selector 46, distribution
Dynamic control for 8 orders via circuit 485
Timing when the regular parameter data DPR is given
The parameter data DPR is updated in synchronization with the
Shift the filter coefficient data COEA1 for the 8th order.
Loaded into the register 97 and weighted data
Latch WIA1 to latch circuit 98 and distinguish between even and odd
Data EOA1 is latched into the latch circuit 99.
Since then, new dynamic control parameter data has been developed.
shift register 97 until data DPR is given.
The memories in latch circuits 98 and 99 are retained. Na
In dynamic mode, the shift register
Of the 16 stages of Star 97, from the 9th to the 16th stage
Dynamic control for 8 orders in 8 stages corresponding to
Store the filter coefficient data of the parameters for
The contents of the 8 stages corresponding to the 1st to 8th stages are set to 0.
I'll keep it. Shift register 9 of each storage circuit 481 to 484
The filter coefficient data output from 7 is the selector
486, where the timing signal TS3
Each channel is selected in turn according to the
Divided and multiplexed. In this way, channels 1 to 4
filter coefficient data is time-division multiplexed.
Then, as A series filter coefficient data COEA, A
series multiplier and accumulator section 41 (fourteenth
(Fig.) is supplied. The latch circuit 98 of each memory circuit 481 to 484
The weighted data output from the selector 487
given, where according to the timing signal TS4
Each channel is selected sequentially and time division multiplexed.
be converted into Channels that are time-division multiplexed in this way
The weighting data WEIA for rules 1 to 4 is the multiplication of the A series.
Supplied to the container and accumulator section 41 (Fig. 14)
be done. The latch circuit 99 of each memory circuit 481 to 484
Even/odd identification data of each latched channel 1 to 4
EOA1 to EOA4 are the steps of the corresponding channel.
parallel to the root memories 401 to 404 (Fig. 14).
given to. <Pitch synchronization output circuit 50: Fig. 16> In FIG. 16, the B input of selector 501
is the A-series multiplier and accumulator section 41 (the
Channel 1 output from Figures 11 and 14)
~4 filtered musical tone signal sample value data
SMA is provided in a time division multiplexed manner. Figure 14
In the latch circuit 85, the flaps of each channel 1 to 4 are
The timing at which the filtered output is captured is the second
The cumulative final time slot (slanted) in the SUM column in Figure 0
line part), and this allows each channel 1
~4 filtered sample value data SMA chip
The Yannel timing is shown in Figure 17.
Ru. A B-series multiplier is connected to the C input of the selector 501.
and output from the accumulator section 43 (Fig. 11)
Filtered musical tone signals of channels 5 to 8
The sample value data SMB is given in a time division multiplexed manner.
It will be done. Channel timing for this data SMB
is as shown in FIG. The A input of selector 501 has 8 stages of shifting.
The output of the selector register 502 is given, and the selector
The output of 501 is input to the shift register 502.
It will be done. This selector 501 and shift register 50
2 is a filtered sample of each channel 1-8
channel value data to the channel timing of PS1 in Figure 3.
High-speed processing in one time slot unit as shown in Fig.
To perform time division multiplexing according to time division timing
belongs to. Tie from decoder 56 in FIG.
At Muslot 57, 13, 26, 46
Timing signal 1REGLDA that becomes “1” and time
“1” in slots 11, 31, 44, 64
A timing signal 1REGLDB is generated, and this
This is the B selection control input of selector 501 in Fig. 16.
SB and C selection control input SC. This is it
out of the data SMA given to the B input.
The data of channel 1 is in time slot 57 (this
is the channel timing of PS1 shown in Figure 3.
(corresponding to the timing of channel 1).
channel 2 data is selected in the time slot.
13 (timing of channel 2 of PS1 in Figure 3)
channel 3 data is selected in
Slot 26 (channel 3 of PS1 in Figure 3)
timing) and channel 4 data.
is time slot 46 (PS1 channel in Figure 3).
(timing of channel 4). Also, C input
Out of the data SMB given to the power channel
5 data is time slot 11 (PS in Figure 3).
1 channel 5 timing), and the channel
The data of channel 6 is in time slot 31 (3rd
Select at the timing of channel 6 of PS1 in the diagram)
and the channel 7 data is transferred to time slot 4.
4 (timing of channel 7 of PS1 in Figure 3)
is selected, and the data of channel 8 is time slotted.
64 (Tie of channel 8 of PS1 in Figure 3)
selected). Timing signals 1REGLDA and 1REGLDB are set to NOR
The signal inverted by the circuit 503 is the A of the selector 501.
Provided to selection control input SA. Therefore, the above
The data is taken into the shift register 502 at each timing.
Filtered sample value data for each channel
At other times, the shift register
The data is cyclically held in the data file 502. The output of the shift register 502 is sent to the selector 504
is given to the A input of The output of selector 504 is
is input to the 8-stage shift register 505.
Ru. The output of the shift register 505 is the selector 50
It is returned to the input side via the B input of 4. selector
504 and shift register 505 are digital
Synchronize the output musical tone signal of the filter with that pitch.
This is for resampling. selector
The A selection control input SA of 504 has an input interface.
source 38 (Figure 12)
Pitch synchronization signal PS1D is delayed by 8 time slots
It is input via circuit 506. In Figure 12, the pitch synchronization signal PS1 is
64 stage shift register via circuit 51
100 is input. This shift register 100
The pitch synchronization signal delayed by 24 time slots is
Input to AND circuit 101, 40 time slots
The delayed one is input to the AND circuit 102,
The one delayed by 48 time slots is AND circuit 1
03 and delayed by 64 timeslots.
is input to the AND circuit 104. each and times
The other inputs of paths 101 to 104 include the devices shown in FIG.
Timing signal PSS1 generated from coder 56
~PSS4 are respectively input. Each AND circuit 101
The outputs of ~104 are given to the OR circuit 105 and
An extended pitch synchronization signal PS1D is obtained. each message
The timing of occurrence of PSS1 to PSS4 is shown in Figure 13.
This is as shown in Nikatsuko's writing. Hey there
For example, the display “1y8” means 8 time slots.
The signal “1” is generated at the first time slot in the cycle.
to show that it is alive. Therefore, the timing signal PSS
In the case of 1, it is "1y8, 3y8", so 8 times
At the 1st and 3rd time slot in the lot cycle
A signal "1" is generated in each case. Each signal in Figure 13
Display inside the box for PSS1 to PSS4 and PS in Figure 3
It is clear if you refer to the channel timing of 1.
As shown, signal PSS1 is a channel in PS1.
becomes “1” at the timing of signals 1 and 3, and PSS2 becomes “1”.
At the timing of channels 2 and 6 on PS1
“1” and PSS3 is the channel in PS1
It becomes “1” at the timing of 3 and 7, and PSS4 becomes
At the timing of channels 4 and 8 on PS1
It becomes “1”. As a result of the above, the pitch synchronous communication of channels 1 and 5 is completed.
No. PS1 has 24 time slots, 2 and 6 PS1 have 40
Time slot, 3 and 7 PS1 is 48 time slot
4 and 8 PS1 have 64 time slots, respectively.
Delayed pitch synchronization signal PS1D
shall be. In this way, the delay time depends on the channel.
The reason for the difference is that adaptive digital files
Each channel 1 in data device 21 (Fig. 11)
~4, Did you adjust to the difference in calculation timing from 5 to 8?
It is et al. Returning to Figure 16, the delayed pitch synchronization signal
PS1D has 8 additional time slots with delay circuit 506
is delayed and given to input SA of selector 504.
Ru. Selector 504 selects the signal of a certain channel.
When PS1D is “1”, the filter of that channel
The completed sample value data is transferred to the shift register 502.
and input it to the shift register 505.
Otherwise, the contents of the shift register 505
is held in circulation via the B input of selector 504.
Ru. In this way, selector 504 and shift register
In the circuit of the controller 505, the filter of each channel is
sampled data occurs on that channel.
resampled in sync with the pitch of the musical note.
It will be done. <Switching between pitch synchronous/asynchronous filter calculation> From the microcomputer interface 44 (Figure 11)
The same pitch applied to the OR circuit 51 in FIG.
The period/asynchronous designation signal PASY is synchronized with pitch.
When performing a router operation, it is always “0” and the input input
Tough Ace 38 responds to pitch synchronization signal PS1.
Filter operation request signals φF1 to φF8 and delay
generates pitch synchronization signal PS1D. Therefore,
When the pitch synchronization signal PS1 is generated, that is, when the pitch synchronization signal PS1 is generated,
Synchronized with the pitch of the musical tone signal to which the filter should be applied.
Digital filter calculation is performed at the sampling period.
It will be done. As a result, the obtained filter characteristics are
It becomes a moving formant. When performing filter calculation without pitch synchronization
always sets the pitch synchronous/asynchronous designation signal PASY.
Set to “1”. Therefore, the OR circuit 51 in FIG.
The output of is regardless of the presence or absence of pitch synchronization signal PS1.
It is always “1”. Therefore, the input interface
Base 38 corresponds to each filter operation cycle (64 times).
Filter calculation request signal at a constant cycle for each lot
Generates φF1 to φF8 and signal PS1D. Therefore,
Sampling frequency in digital filter calculation
The wave number is constant (for example, 50kHz) regardless of pitch.
The resulting filter characteristics are fixed formants.
becomes. <Example of filter characteristics> Filter characteristics that can be realized by the above embodiment
An example is shown in FIGS. 22 to 27. In Figure 22, the order of the filter is set to an odd number (31st order).
Shows an example of the characteristics obtained when set.
It realizes high-pass filter characteristics.
Ru. fs/2 is 1/2 of the sampling frequency fs,
When in pitch cycle mode, the pitch is synchronized with the pitch of the musical note.
frequency, and is constant when in pitch asynchronous mode.
It is a constant frequency. In Figure 23, the order of the filter is set to an even number (32nd order).
Shows an example of the characteristics obtained when set.
It realizes low-pass filter characteristics.
Ru. Figure 24 shows the time in dynamic mode.
This shows an example of filter characteristics that change. child
In the case of the example, the tone generator section 18 generates
The sound source waveform signal to be played is f (fuorte), that is, the strongest key.
Assuming that it corresponds to tatsuchi, p (piano)
touch, mp (mezzo piano) touch, mf (mezzo)
The musical tone signal corresponding to each touch of Fuorte) is
The field obtained by filtering the sound source waveform signal
It shows the temporal change in the filter characteristics when Time
The columns in between indicate the types to be switched to for each filter characteristic.
The timing is indicated by the time from the start of pronunciation.
Ru. The numbers in the filter characteristic diagram indicate the change point.
It shows the frequency, and the unit is Hz. In addition,
Assume that the pitch of the musical tone to be played is F2. Figure 25 is played with the touch of f (fuorte).
Spectral envelope of the original waveform of the F2 piano sound
Figure 26 shows the p (piano) tap.
Specifies the original waveform of the F2 piano sound played in Tutsi.
The vector envelope is shown. Figure 25 original
The waveform is at the Oms point in the column p (piano) in Figure 24.
Obtained by filtering with the filter characteristics of
The second spectral envelope of the musical tone signal is
It is as shown in Figure 7, and the source of p touch shown in Figure 26.
It is similar to the spectral envelope of the waveform.
I understand. <Example of change> The pitch synchronization output circuit 50 shown in FIG.
channel using the shift registers 502 and 505.
I am performing pitch synchronization processing in time division, but this
However, memory circuits can be set up in parallel for each channel.
Even if you perform pitch synchronization processing in parallel,
good. In the above embodiment, the digital filter is
We used an FIR filter with numerical symmetry, but this
Even when using an FIR filter with asymmetric coefficients,
good. In addition, the filter model is not limited to FIR, but also IIR (innocent).
limited impulse response) or other types.
You can also do this. The storage format of the parameter memory shown in Figure 21
-Matsuto is not limited to this, and various changes are possible.
It is. For example, do not adopt such a hierarchical structure.
You can do whatever you like. Also, the method of addressing the parameter memory is shown above.
Not limited to the procedure shown in the example below, various changes are possible.
It is Noh. For example, in the example, the key group
access the table first, then the Tatsuchi group table.
accessing the bull, even if it is the other way around.
good. In addition, in FIG. 15, the program memory 45
1. Microprogram with readout procedure stored in advance
A ramming method is adopted, which allows parameter
I am trying to read memory 47, but this
It is not possible to use a microprogram method such as
Complete hardwired circuit or complete software
The readout is controlled by the hardware program.
You may do so. In addition, in the above embodiment, in a multitone electronic musical instrument,
Although the lever invention is applied, it is a single-note electronic musical instrument.
Of course, it can also be applied to
Ru. In addition, not only dedicated electronic musical instruments, but also musical tone signal generators can be used.
This invention generally applies to devices with raw or processing functions.
can be applied. In the above embodiment, the adapter is connected to the tone generator.
The data input to the digital filter device
The digital musical tone signal sample value data itself is
It was sampled in sync with Tsuchi.
However, it is not limited to this. example
For example, sampling with a pitch asynchronous fixed sampling period
Digitally converts the pulled digital musical tone signal into
Even when inputting to a filter device, the pitch synchronization signal
This input digital musical tone signal is sampled by
Filter performance synchronized with pitch while re-ringing
All you have to do is perform arithmetic operations. In addition, in the above embodiment, the pitch synchronization signal generation circuit
is contained within the tone generator, where
The generated pitch synchronization signal is converted into an adaptive digitizer.
I am trying to introduce it into a filter device, but this
Not limited to this. For example, sample data synchronized to pitch.
A digital musical tone signal with a ring period is digitized.
When inputting to the filter, this digital musical tone
To detect changes in sample value data of a signal
Generate a pitch synchronization signal, thus generated
Control filter calculation operation by pitch synchronization signal
You may also do so.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an overview of the invention, Fig. 2 is a block diagram showing the overall configuration of an electronic musical instrument according to an embodiment of the invention, and Fig. 3 shows the timing of main signals in the embodiment. Timing chart, Figure 4 is a block diagram showing an example of the pitch synchronization signal generation circuit included in the tone generator of Figure 2, Figure 5 is a block diagram showing the basic configuration of the FIR filter, Figures 6 and 7. The figure shows linear phase FIR
Graphs showing an example of the symmetry of the impulse response in a filter when the order N is an odd number and when the order N is an even number. Figures 8 and 9 show examples of frequency response characteristics in a linear phase FIR filter when the order N is an odd number. 10 is a flowchart showing an example of the procedure for determining the filter coefficient, FIG. 11 is a block diagram showing an example of the adaptive digital filter device in FIG. 2, and FIG. 11 is a block diagram showing an example of the input interface in FIG. 11, FIG. 13 is a block diagram showing an example of the timing signal generation circuit in FIG. 11, and FIG. 14 is a block diagram showing the state memory, multiplier, and accumulator in FIG. 11. 15 is a block diagram showing an example of the FIR type digital filter circuit.
The figure is a block diagram showing an example of the parameter processing unit and parameter supply circuit in Fig. 11, Fig. 16 is a block diagram showing an example of the pitch synchronization output circuit in Fig. 11, and Fig. 17 is a block diagram showing an example of the pitch synchronization output circuit in Fig. A timing chart showing an example of signal generation, and FIG. 18 is used to explain the basic operation of FIR type filter operation when realizing filter characteristics consisting of an even number order (32nd order) in the digital filter circuit shown in FIG. 14. Figure 19 is a schematic diagram for explaining the basic operation of FIR type filter operation when realizing odd-order (31st order) filter characteristics in the same digital filter circuit, and Figure 20 is shown in Figure 14. A diagram showing the filter calculation operation timing for 8 channels in the A and B2 series digital filter circuits, Figure 21 is similar to Figures 11 and 15.
FIGS. 22 and 23 are diagrams showing an example of the storage format of the parameter memory shown in the figure, and FIGS. 22 and 23 show examples of filter characteristics realized in the embodiment of the present invention shown in FIGS. FIG. 24 is a diagram showing an example of the temporally changing filter characteristics realized in the dynamic mode of the same embodiment for several touch intensities, and FIGS. The figure shows the spectral envelope of the original waveform of the F2 note of the piano when played with Folte Touch and when played with Piano Touch, respectively. Figure 27 is obtained when the original waveform of Folte Touch is filtered with the filter characteristics of Piano Touch in the above example. FIG. 3 is a diagram showing an example of a spectral envelope of a musical tone signal. 110... pitch synchronization signal generating means, 111...
...Digital filter circuit, 10...Keyboard, 11
...Key touch detector, 18...Tone generator, 19...Pitch synchronization signal generation circuit, 21,2
2...Adaptive digital filter device, 4
0, 42... State memory, 41, 43... Multiplier and accumulator section, 45... Parameter processing unit, 47... Parameter memory, 50... Pitch synchronization output circuit.

Claims (1)

[Scope of Claims] 1. pitch synchronization signal generation means for generating a signal synchronized with the pitch of a digital musical tone signal; A musical tone signal processing device comprising a digital filter circuit that performs filter calculation at a sampling period. 2. A pitch synchronization signal generation means for generating a signal synchronized with the pitch of a digital musical tone signal, and a pitch synchronization signal generating means for specifying whether filter operation should be performed in synchronization with the pitch of the musical tone or asynchronously.
means for generating an asynchronous designation signal; and a means for inputting the digital musical tone signal and generating a sampling period synchronized with the pitch synchronization signal generated from the pitch synchronization signal generation means or a predetermined common frequency according to the pitch synchronization/asynchronous designation signal. A musical tone signal processing device comprising a digital filter circuit that performs a filter operation in one of sampling periods.