JPH0313785Y2 - - Google Patents

Description

[Detailed explanation of the invention] [Industrial application field] This invention is used by being built into electronic equipment.
This relates to an alarm device whose purpose is to display and notify the occurrence of a malfunction due to a drop in the power supply voltage of a CPU (Central Processing Unit). [Conventional technology] The operating program is permanently stored in the CPU.
It includes ROM and a RAM function that can be written and erased by external operations.RAM in particular has the property of erasing its stored contents when the power supply voltage drops below a specified value, which can also cause malfunctions. To prevent this, in many CPUs the power supply voltage approaches the minimum allowable value and the halt (HLT) input is disabled.
When it goes low, the halt function is activated to protect the memory contents. At this time, a warning pulse is output to the warning buzzer output port, making it possible to detect an abnormality in the power supply voltage.
This works well when the voltage gradually decreases, such as when the battery power supply deteriorates, but if the voltage suddenly decreases for some reason, it will go into a halt state, but a warning pulse will be generated. Since the operation is stopped without any adjustment, the user may misunderstand it as a handling problem and spend unnecessary effort. [Problem to be solved by the invention] This invention was devised to solve the above-mentioned problem, and no matter how low the power supply voltage supplied to the CPU becomes, a warning signal is always output when the halt state occurs. The purpose is to provide a circuit that [Means for solving the problem] In a CPU that has a function of halting and warning when the voltage drops below the stable operating voltage, a pull-down resistor is connected to the alarm buzzer output port, a first blocking oscillator that oscillates a low frequency, and a voice band a second blocking oscillator that oscillates at a frequency of , a transistor that performs a switching operation when the output of the first blocking oscillator is supplied, and a transistor that changes the oscillation frequency of the second blocking oscillator when the transistor is in a conductive state. Alarm device connected to configured alarm signal circuit. [Example] FIG. 1 is a schematic diagram of the present invention. The input terminal 21 of the alarm device 2 is connected to the CPU 1 halt operation warning buzzer output port 11, and the alarm device 2 consists of a blocking oscillator 22 and a buzzer 23, and when the input terminal 21 is at H level, the oscillation operation is stopped. However, at L level, it oscillates and the buzzer 23 emits an alarm sound. The CPU 1 warning buzzer output port 11 is at H level during normal operation, and is in a high impedance state during a halt state , so the oscillator 22
It is possible to control the operation of As the alarm display means of the alarm device 2 , a light emitting indicator may be used instead of the buzzer 23, or both may be used in combination. In actual operation, if a common power source is used, the minimum operating voltage of the alarm device 2 must be lower than the CPU 1 halt operating voltage, and if possible, it is desirable to supply it from a separate power source. FIG. 2 is a circuit example of the alarm device of the present invention. In the figure, the blocking oscillator of alarm device 2 is 22
It combines two transmitters with different frequencies, A and 22B, to give it a distinctive tone.The configuration of each circuit uses two NOR gates, and the warning buzzer output port 11 becomes high impedance when the CPU is in halt operation. Since it is pulled down by _R1 and becomes the L level, both the front and rear stages operate as inverters, and when the CPU 1 is operating normally, the input terminal 21 is at the H level.
level, the previous-stage gate becomes inactive and oscillation stops. The oscillation frequency of the circuit constants shown in FIG. 2 is approximately 4 kHz when the transistor TRI is ON on the blocking oscillator 22A side, and approximately 2 kHz when the transistor TRI is OFF. Blocking oscillator 22B side is approximately 5Hz
It is. FIG. 2 is a circuit diagram of a configuration in which the buzzer 23 generates sounds by switching between 4kHz and 2kHz tones in a 3Hz cycle. [Effects of the invention] As described above, the present invention provides an external control system that prevents the CPU from issuing an alarm during the halt operation that protects the memory contents of the RAM of the CPU, thereby preventing unnecessary confusion for the users of the device. Connect the alarm device to the warning buzzer output port of the CPU, convert the internal impedance change during CPU halt operation to the output level of the warning buzzer output port, and operate the blocking oscillator of the external alarm device to alternate between two types of sounds. There is no chance of a warning being misinterpreted.

[Brief explanation of the drawing]

Figure 1 is a block circuit diagram of the alarm device of the present invention.
FIG. 2 is a circuit diagram of an alarm device showing an embodiment of the present invention. 1 ...CPU, 11...Warning buzzer output port,
2...Alarm device, 21...Alarm device input terminal, 2
2, 22A, 22B...Blocking oscillation circuit,
23...buzzer.

Claims (1)

[Scope of utility model registration request] In a CPU that has the function of halting and outputting a warning signal when the voltage drops below the stable operating voltage,
a pull-down resistor from an alarm buzzer output port, and a first blocking oscillator that oscillates a low frequency when the alarm buzzer output port is at a low level;
and a second blocking oscillator that oscillates a frequency in the audio band; a transistor that performs a switching operation when the output of the first blocking oscillator is supplied; and when the transistor is in a conductive state, the oscillation frequency of the second blocking oscillator is changed. In a halt state, the first and second blocking oscillators each oscillate, and the second blocking oscillator alternately outputs different sounds by the switching operation of the transistor to generate an alarm. An alarm device characterized by: