JPH0314242B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL (abbreviation for phased lock loop) type voltage controlled oscillator, and particularly to a voltage controlled oscillator driven at a low voltage.

FIG. 1 is an electrical circuit diagram of a conventional voltage controlled oscillator. The voltage controlled oscillator in FIG. 1 is, for example,
It has a free-running oscillation frequency of 76KHz. and,
Such a voltage controlled oscillator may be used in a PLL system circuit for phase comparison of a 19KHz pilot signal in an FM stereo multiplex circuit. In such a case, the free-running oscillation frequency of the voltage controlled oscillator is frequency-divided to 38KHz, further divided to 19KHz, and then phase-compared by a phase comparison circuit. Here, the circuit operation of the voltage controlled oscillator shown in FIG. 1 will be explained. This voltage controlled oscillator is combined with a current amplifier (not shown). That is, a current amplified output of the phase comparison output is applied to the input terminal T1 from a current amplifier. In this state, when the fourth transistor Q4 is currently in a cut-off state, the first transistor Q1 is conductive and the third transistor Q3 is also conductive. As a result, the emitter of the third transistor Q3 is connected to the first transistor Q from the power supply voltage Vcc.
The saturation voltage Vsat between the collector and emitter of transistor Q3 and the voltage between the base and emitter of the third transistor Q3
The voltage obtained by subtracting Vbe appears. Therefore, the voltage at the emitter of the third transistor Q3 is connected to the base of the fifth transistor Q5 through the first resistor R1.
A voltage divided by the third resistor R3 and the third resistor R3 is applied as the first reference voltage on the low level side. Next, since the fourth transistor Q4 is cut off, the capacitor C1 forming the charging/discharging circuit is in a state of natural discharge. This natural discharge causes the 13th transistor Q13 to
When the base voltage of the fifth transistor Q5 becomes lower than the base voltage of the fifth transistor Q5, the seventh transistor Q7 and the tenth transistor Q1
0 and the 10th transistor Q
Since the comparison level of transistor No. 10 becomes lower, the seventh transistor Q7 becomes conductive, and the tenth transistor Q10 becomes conductive.
is blocked. Due to this conduction of the seventh transistor Q7, current is drawn from the sixth transistor Q6 toward the seventh transistor Q7 in the sixth, ninth, and eleventh transistors Q6, Q9, and Q11 forming the current mirror circuit, and as a result, current is drawn from the sixth transistor Q6 toward the seventh transistor Q7. Current also flows through the ninth transistor Q9 and the eleventh transistor Q11, which are not present. Then, since the tenth transistor Q10 is in the cutoff state, the current from the ninth transistor Q9 flows to the fourth transistor Q4. This makes the fourth transistor Q4 conductive. Due to the conduction of the fourth transistor Q4, current flows through the second and fourth resistors R2 and R4. Then,
The current flows through the fourth resistor R4 to the capacitor C1 of the charging/discharging circuit, and the capacitor C1 is charged.
On the other hand, the first and second resistors R1 and R2 are connected in parallel due to conduction of the fourth transistor Q4, and therefore the base voltage of the fifth transistor Q5 increases. This increased voltage is the second voltage on the high level side.
This becomes the reference voltage. In this state, when the charging voltage of the capacitor C1 rises and exceeds the second reference voltage, the tenth transistor Q10 becomes conductive and the seventh transistor Q7 turns off. When the seventh transistor Q7 is cut off,
Since the sixth transistor Q6 of the current mirror circuit is cut off and no current flows, no current flows from the 9th and 11th transistors Q9 and Q11 either.
However, since the tenth transistor Q10 is conductive, no current flows to the base of the fourth transistor Q4, and as a result, the fourth transistor Q4 is cut off. Due to this interruption, no charging current flows through the capacitor C1 of the charging/discharging circuit, so the charging voltage of the capacitor C1 decreases due to natural discharge, and the base voltage of the thirteenth transistor Q13 decreases accordingly. In this manner, the voltage controlled oscillator free-runs at a frequency responsive to the output from the current amplifier.

In a voltage controlled oscillator that operates in this manner, the free-running oscillation frequency f ₀ changes due to fluctuations in the power supply voltage Vcc, as shown in FIG. That is, as is clear from Fig. 2, in this voltage controlled oscillator, a large peak occurs in the relationship between the power supply voltage Vcc and the free-running oscillation frequency _f0 , and as the power supply voltage Vcc increases, the free-running oscillation frequency decreases. f ₀ goes to a lower value. Conversely, as the power supply voltage Vcc decreases, the free-running oscillation frequency f ₀ increases. However, if this voltage controlled oscillator is of the type that is driven by a single dry cell battery, and the power supply voltage Vcc of the dry cell battery decreases to, for example, about 1 volt due to its use, the power supply voltage Vcc will decrease as shown in Figure 2. Since there is a relationship between and the free-running oscillation frequency _f0 that has a large peak at low power supply voltage Vcc, the oscillation operation of the voltage controlled oscillator becomes extremely unstable. To solve this problem, it would be better to use a stabilized power source, but since the device is driven at a low voltage, this stabilized power source cannot be used. This has resulted in deterioration of separation in the FM stereo multiplex when the power is reduced.

The present invention has been made in view of the above-mentioned circumstances, and the present invention has been made in such a way that the relationship between the power supply voltage Vcc and the free-running oscillation frequency f ₀ is flat, so that the free-running oscillation occurs in response to fluctuations in the power supply voltage. The main purpose is to stabilize the frequency.

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. FIG. 3 is an electrical circuit diagram of an embodiment of the invention, and parts corresponding to those in FIG. 1 are given the same reference numerals. In FIG. 3, reference numeral 1 constitutes a reference voltage setting circuit, and this reference voltage setting circuit 1
are the first, third and fourth transistors Q1, Q3, Q
4 and first, second, and third resistors R1, R2, and R3. The fourth transistor Q4 has a first emitter and a second emitter, and a second resistor R2 is connected to the first emitter, and a fourth resistor R4 is connected to the second emitter. And this fourth transistor Q4
has a function of obtaining the first and second reference voltages (described later) by passing current through the second resistor R2 connected to the first emitter, and through a fourth resistor R4 connected to the second emitter. It also functions as a charging current control transistor by supplying a charging current to a charging/discharging circuit 4, which will be described later. 2 is a comparator, and this cone comparator 2 is the 7th and 10th cone comparator.
Includes transistors Q7 and Q10. 3 is a current mirror circuit, and this current mirror circuit 3 includes 6th, 9th, and 11th transistors Q6, Q9, and Q1.
Contains 1. The ninth transistor Q9 has a function as a conduction control transistor that controls conduction/non-conduction of the fourth transistor Q4 by applying a base current to the base of the fourth transistor Q4. 4 is a charging/discharging circuit, and this charging/discharging circuit 4
includes a first capacitor C1, a seventh resistor R7, a variable resistor, and an eighth resistor R8. This charging/discharging circuit 4 is the fourth
A charging current is applied to the internal capacitor C1 via the transistor Q4.
Q5 and Q13 are the fifth and fifth voltage shift circuits.
13 transistors. 11 and 12 are constant current sources, and Q2, Q8, and Q12 are second, eighth, and twelfth transistors.

C2 is a second capacitor which is a main part of this embodiment, and is a ninth transistor Q9 as a conduction control transistor with respect to the base of the fourth transistor Q4 as the charging current control transistor.
A capacitor is a capacitive element that is connected between a connection point (point A) and a ground point to slow down the rising speed (slew rate) of the voltage waveform at point A.

Next, the operation will be explained. Here, the basic operation of the voltage controlled oscillator of the embodiment is the same as that of the circuit shown in FIG. 1 (as described above) except for the capacitor C2, and thus will be omitted for simplicity of explanation.

Now, if the second capacitor C2 is not provided, the collector of the ninth transistor Q9, that is, A
The voltage waveform at the point changes as shown in the dotted circle C in FIG. 1 due to conduction or non-conduction of the ninth transistor Q9. On the other hand, in this embodiment in which the second capacitor C2 is provided, the voltage waveform at point A changes as shown in the dotted circle D in FIG. Therefore, in the conventional example shown in FIG. 1, the slew rate of the voltage waveform at point A is fast, and its amplitude fluctuates due to fluctuations in the power supply voltage Vcc. The time required to charge the first capacitor C1 fluctuates. This variation in the charging time to the first capacitor C1 results in a variation in the free-running oscillation frequency of the voltage controlled oscillator, since the discharge time constant of the charging/discharging circuit including the first capacitor C1 is constant. Become something.

In contrast, in this embodiment, since the second capacitor C2 is provided at point A, the slew rate of the voltage waveform at point A is slow, so even if the power supply voltage Vcc fluctuates, the first capacitor C2 at point B The charging time to C1 is no longer affected so much, so the charging/discharging operation of the charging/discharging circuit including the first capacitor C1 becomes as expected, and as a result, the power supply voltage
Even if Vcc fluctuates, the free-running oscillation frequency can be extremely stabilized. FIG. 4 is a diagram showing the relationship between the power supply voltage Vcc and the free-running oscillation frequency f ₀ of the voltage controlled oscillator of this embodiment. As is clear from this figure, in this embodiment, the free-running oscillation frequency f ₀ with respect to fluctuations in the power supply voltage Vcc is almost flat, so even if the fluctuations, for example, the power supply voltage Vcc decreases due to dry battery consumption, the voltage control The free-running oscillation frequency f ₀ of the oscillator becomes stable without being affected by its decrease.

As described above, according to the present invention, since the second capacitor is configured to be connected between the common connection point between the base of the fourth transistor and the collector of the ninth transistor and the ground point, the common connection point The slew rate of the voltage waveform can be slowed down, resulting in a nearly flat relationship between the supply voltage and the free-running oscillation frequency, which allows the free-running It became possible to stabilize the oscillation frequency. In addition, this makes it possible to apply this voltage-controlled oscillator to the PLL system of an FM stereo multiplex circuit, and to use a single dry battery as a power source for low-voltage operation, even when the power decreases due to battery depletion. This eliminates the problem of deterioration in separation, and also makes it possible to downsize the set.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional example, Fig. 2 is a diagram of the relationship between free-running oscillation frequency f ₀ and power supply voltage Vcc in a conventional example, Fig. 3 is a circuit diagram of an embodiment of the present invention, and Fig. 4 is a diagram of this embodiment. FIG. 3 is a relationship diagram of free-running oscillation frequency f ₀ versus power supply voltage Vcc according to an example. 1 is a reference voltage setting circuit, 2 is a comparator, 3
is a current mirror circuit, and 4 is a charge/discharge circuit. Q4 is the fourth transistor (transistor for controlling charging current), and Q9 is the ninth transistor (transistor for controlling conduction).

Claims (1)

[Claims] 1. Reference voltage setting circuit 1, charging/discharging circuit 4, comparator 2, current mirror circuit 3, and second
The reference voltage setting circuit 1 includes a capacitor C2, and includes a fourth transistor Q4 as a charging current control transistor, which is provided with a first emitter and a second emitter.
A reference voltage is generated and output based on the first emitter output corresponding to the cutoff/conduction state of transistor Q4, and a charging current is output from the second emitter via the voltage source (Vcc) when it is conductive. The discharge circuit 4 has a first capacitor C1, and the first capacitor C1 is charged with the charging current from the second emitter, and when the charging current is not applied, the first capacitor C1 is charged with the charging current from the second emitter. C1 performs a natural discharge operation, and the comparator 2 includes a seventh transistor Q7 whose base is supplied with the reference voltage from the reference voltage setting circuit 1, and a tenth transistor Q10 whose base is supplied with the output of the charge/discharge circuit 4. The emitters of both transistors Q7 and Q10 are connected in common, and the magnitude of the input to each base is compared to conduct or cut off the current mirror circuit 3. , has a sixth transistor Q6 whose emitters are commonly connected to each other, and a ninth transistor Q9 as a conduction control transistor, and the base and collector of the sixth transistor Q6 are connected, and the collector is connected to the seventh transistor Q7.
The ninth transistor Q9 has an emitter and a base connected to the emitter and base of the sixth transistor Q6, and a collector connected to the base of the fourth transistor Q4 and the tenth transistor. Q1
The second capacitor C2 is commonly connected to the collector of the fourth transistor Q4.
A voltage controlled oscillator, characterized in that the voltage controlled oscillator is connected between a common connection point between the base of the transistor Q9 and the collector of the ninth transistor Q9, and a ground point.