JPH0314272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an input television signal that enters from the antenna input of a color television receiver and to other video equipment such as a video tape recorder, a video disc player, a television camera, a personal computer, etc. This invention relates to a television receiver that simultaneously displays signals from a computer or the like on one screen.

Conventional configurations and their problems In recent years, the connection of various video equipment such as video tape recorders, video disk players, television cameras, personal computers and general television receivers has become popular, and the new media has further developed. I think it will go. On the other hand, 1
Previous attempts have been made to display two different images simultaneously on a single television receiver.

FIG. 1 shows a specific screen display example, showing the display state of a main screen 2 and a sub-screen 3 on a television receiver 1.

FIG. 2 shows an example of its configuration. In the figure, the signal input from the antenna 11 is transmitted to the tuner 12,
The video and audio signals that have passed through the video intermediate frequency circuit 13 are demodulated, and the demodulated video and audio signals are
Video and audio signals from other video equipment 14 are applied to the switching circuit 16, and based on a command from the switching command circuit 15, for example, a remote control transmitter, the switching circuit 16 outputs a color/video signal processing circuit 17, a synchronization circuit 18, an audio The first signal supplied to the circuit 19, the color/video signal processing circuit 24, the synchronization circuit 28,
Two of the second signals supplied to the audio circuit 32 are output. The first signal becomes the main screen 2 in FIG. 1, and the second signal becomes the sub-screen 3 in FIG.

The signal that has passed through the color/video signal processing circuit 24 is digitized by the A/D converter 25, and the synchronization signal output from the synchronization circuit 28 is counted to determine whether the first field is the second field or not. A circuit 31 that counts the synchronization signal output of the circuit 18 and determines whether it is the first field or the second field.
The two discrimination circuit outputs pass through the interlace correction circuit 33, and from the synchronization signal of the child screen 3, it is written to the 1 field memory 26 with a clock synchronized with it, and it is read out with a clock synchronized with the synchronization signal of the main screen 2, and D/A conversion is performed. The two-screen creation circuit 22 inserts the signal of the sub-screen 3 into the signal of the main screen 2 and displays the video signal on the picture tube 23.

Television video signals use an interlaced system (separated into odd and even fields, which appear alternately on the time axis and fill in the gaps alternately on the picture tube). FIG. 3 shows an example of the phase relationship between the child screen signal and the main screen signal. In this case, writing and reading to the 1-field memory 26 overlap, and in this memory b ₁ ' the sub-screen
b ₁ information (even field 1), and the second half
The contents of a ₁ (odd field 1) before b ₁ are read out to a _{1 '} .

Figure 4~ shows the reproduction state of the sub-screen on the picture tube.The horizontal line is the scanning line, the numbers on the left indicate the content, and the odd (even) on the right indicates the scanning line of the odd (even) field. It shows.

Fig. 4 shows that the contents written to the 1-field memory 26 are only odd fields or only even fields, and when the same field as the written field is read out, there is no problem with sub screen 3.
is played.

However, when writing and reading are performed as shown in FIG. 3, the contents become wavy and unsightly as shown in FIGS. If , the lower side will be wavy, and if , the upper side will be wavy.

Figure 4 shows a case where the fields of the parent and child are the same (odd and odd or even and even), and the fields of the parent and child are different halfway (odd and even or even and odd).
Figure 4 shows cases in which the fields of the parent and child are different until the middle (odd and even or even and odd), and the fields of the parent and child are the same from the middle (odd and odd or even and even), and the fields of the parent and child are the same. The time is normal, but when the fields of the parent and child are different, it becomes wavy.

Here, a method of correction in the case of FIG. 4 will be described.
Figure 4 shows the case where the read address is delayed by one in an odd field from when the interlace is reversed, and Figure 4 shows the case where the read address is advanced by one in an even field from the time when the interlace is reversed. There is something strange about the reversal, but after that it becomes normal.

In this way, in FIG. 2, the sub-screen field discrimination circuit 29
and an interlace correction circuit 33 that performs line correction as shown in FIG. 4 on the output of the main screen field discrimination circuit 31 from the synchronization signal of the main screen video signal.
to control the memory controller 30.

This is effective for normal television video signals, but video signals from personal computers and the like are not interlaced and are sent in a method called non-interlace. If the main screen is a non-interlaced signal, performing the above-mentioned interlace correction will result in a screen that is difficult to view. This is because in the case of non-interlaced signals, the horizontal synchronization pulses in the vertical synchronization signal are integer multiples (262 or 263), making it difficult to distinguish between the first and second fields, making it difficult to see the sub-screen. It will become.

OBJECT OF THE INVENTION The object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to provide a television receiver that can normally display a sub-screen regardless of whether the main screen signal is an interlaced signal or a non-interlaced signal. shall be.

Structure of the Invention In the present invention, in a two-screen television receiver, an interlace correction circuit is operated when the main screen is an interlace signal, and is stopped when the main screen is a non-interlace signal. As a result, the image on the sub-screen appears stable.

DESCRIPTION OF EMBODIMENTS As an example of the present invention, as shown in FIG. When there is no difference, the interlace correction circuit is stopped.

Further, as another example of the present invention, there is a method as shown in FIG. 6 in which the interlace correction circuit 33 is stopped by an external circuit when a non-interlaced signal from a personal computer or the like is received on the main screen. 34 is an interlace correction circuit switching circuit. 35 is a personal computer switching circuit, which is turned on and off when input from a personal computer or the like.

By operating the interlace correction circuit 33 for interlaced signals and stopping the interlace correction circuit 33 for non-interlaced signals, it is possible to obtain a good child screen image in either case.

Effects of the Invention As described above, according to the present invention, when the main screen signal is an interlaced signal, the sub screen is displayed normally by correcting the interlace. Furthermore, if the main screen signal is a non-interlaced signal, there are no odd or even fields, so the child screen is displayed normally.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a specific screen display example of a television receiver to which the present invention is applied, FIG. 2 is a block diagram of a conventional two-screen television receiver, and FIG. 3 is a main screen signal. FIG. 4 is a front view showing the state of reproduction of the sub-screen on the picture tube, and FIGS. 5 and 6 are each a television receiver according to an embodiment of the present invention. FIG. 12... tuner, 13... video intermediate frequency circuit, 14... external video equipment, 16... switching circuit,
17, 24... Color image processing circuit, 18, 28...
Synchronous circuit, 22... Two-screen creation circuit, 23... Picture tube, 25... A/D converter, 26... Memory,
27...D/A converter, 29...Small screen field discrimination circuit, 30...Memory controller, 31
...Main screen field discrimination circuit, 33...Interlace correction circuit, 34...Interlace correction circuit switching circuit.

Claims (1)

[Claims] 1. A first synchronization circuit that receives as input a first signal constituting the main screen and performs synchronous separation; and a second synchronization circuit that receives as input a second signal that constitutes the child screen and performs synchronous separation. a second video signal obtained from the second signal;
an A/D converter that performs D conversion; a main screen field determination circuit that counts the output synchronization signal of the first synchronization circuit and determines whether it is the first field or the second field; and the output of the second synchronization circuit. A sub-screen field discrimination circuit counts synchronization signals and determines whether the field is the first field or the second field, and a second clock synchronized with the output synchronization signal of the second synchronization circuit outputs the A/D converter. a storage device that reads the stored data using a first clock synchronized with the output synchronization signal of the first synchronization circuit; and a D/A converter that D/A converts the signal read from the storage device. and a first signal constituting the main screen obtained from the first signal.
A television receiver comprising: a two-screen creation circuit that inserts a video signal constituting a sub-screen output from the D/A converter into the video signal of the D/A converter and displays it on a receiver means; and the main screen field determination circuit. an interlace correction circuit which receives the output signal of the child screen field discrimination circuit, detects a difference in field polarity between parent and child screens, and controls readout of the storage device; and receives the output signal of the main screen field discrimination circuit, A television receiver comprising: prohibition means for prohibiting correction control by the interlace correction circuit when a first video signal constituting a main screen is a non-interlace signal.