JPH0314364B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a digital tank circuit that extracts a single frequency component from an input analog signal.

[Overview of prior art and its drawbacks]

Conventional digital tank circuits consist of means for converting analog signals into sampled binary codes and digital filters including adders, multipliers, and delays. However, the multipliers used in digital filters have a complicated structure and require four multipliers, which has the disadvantage of increasing the cost of the device. Another disadvantage is that the more an attempt is made to sharpen the peak at the center frequency in order to improve the profit characteristics of the digital filter, the more the influence of quantization errors generated by the multiplier cannot be ignored.

[Purpose of the invention]

One object of the invention is therefore to provide a digital tank circuit that does not require the use of multipliers.

Another object of the present invention is to obtain a digital tank circuit with less quantization error.

[Structure of the invention]

In order to achieve the above object, the present invention is an improvement in which the sampling frequency is appropriately selected to eliminate the need for a multiplier, and a quantization error canceling circuit is added to the above-mentioned improved part. It is.

That is, according to the present invention, with reference to FIG. 1 showing the configuration of a first embodiment of the present invention, there is provided a means for converting an analog signal into a binary code sampled at a frequency _S , and a delay time of said sampling. In a tank circuit consisting of a digital filter that extracts the timing of the center frequency _O from the binary code using a delay means corresponding to two frequency cycles 1/ _S , the sampling frequency _S is set to the center frequency. _O , and the digital filters 33 are arranged in series in the same direction, with n being a positive integer, and the intermediate point is the delay means 39,
first and second adders 41 and 42 connected to the inputs of the first adder 41;
a third adder 43 connected to one input of
and an n-bit right shift 37 which receives the binary code and sends its output to the other input of the first adder 41;
a bit inverter 34 and an n-bit right shifter 3 which commonly receive the outputs of the delay means 39, 40 and send the outputs to two inputs of the third adder 43, respectively;
5 parallel circuits, a bit inverter 36 which receives the outputs of the delay means 39 and 40 and sends the output to the second adder 42, and a bit inverter 36 which receives the output of the second adder 42 and whose output is at the center frequency _O. A digital tank circuit is obtained, characterized in that it has a 1-bit right shift 38 to obtain timing.

Further, according to the present invention, with reference to FIG. 1 and FIG. 2 showing the configuration of the second embodiment, the digital tank circuit according to the first invention is mainly used, and the delay means 39 of the tank circuit is .
8, bit inversion 47, and said delay means 39,
additional delay means 4 having substantially the same delay time as 40 and sending an output to the input of said fourth adder 44;
A digital tank circuit characterized by adding a series circuit in which 5 and 46 are arranged in the order described is obtained.

〔Effect of the invention〕

With the above-described structure, the present invention can replace four multipliers with complex configurations with one bit shift circuit and one bit inverting circuit with simple configurations, greatly simplifying the device configuration, and requiring additional circuitry. This effectively reduces the quantization error component contained in the output.

[Specific example of conventional technology]

FIG. 3 is a diagram showing the configuration of a digital tank circuit according to the prior art. Signal a is a high-frequency analog signal that has been converted in advance so that it strongly contains the component of the center frequency _O to be extracted. Here, the above-mentioned conversion means applying full-wave rectification in the case of a bipolar signal, and applying full-wave rectification after differentiation in the case of an NRZ signal. The high frequency analog signal obtained in this way is input to the comparator 11, sliced and converted into a 0-1 signal, and further processed by the sampler 11.
2, the signal is sampled at a frequency _S and input to the digital filter 13. Note that instead of the above method, there is also a method of sampling the high frequency analog signal with a sampler and then quantizing it with an A/D converter. However, the A/D converter has a complicated structure.

The digital filter 13 includes multipliers 14, 15, 16, which use a ₁ , a ₂ , b ₁ , and b ₂ as multiplication coefficients, respectively.
17, bit shifters 18 and 19 that shift bits by c and d, respectively, delayers 20 and 21 whose delay time is the sampling period 1/ _S , and adders 22, 23, 24, and 25. .
This circuit is designed so that the gain characteristics of the digital filter 13 have a sharp peak at the center frequency _O of the tank circuit by adjusting the multiplication coefficients of the four multipliers 14 to 17. Therefore, as mentioned above, the conventional device requires as many as four multipliers with a complicated configuration, and the influence of quantization errors generated by the multipliers cannot be ignored.

[Example of the present invention]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. The process up to the point where the high frequency analog signal a is converted into a 0-1 signal by the comparator 31, sampled by the sampler 32, and inputted to the digital filter 33 is exactly the same as the conventional case shown in FIG. To briefly explain the transfer function for later explanation, the root of the denominator of the transfer function H(z) is called the pole p, and at this point the denominator is 0, that is, the gain is ∞. In the digital filter, the passing frequency of the signal (in this case, the center frequency _O is selected as the pole frequency. Therefore, the transfer function H(z ) is expressed as H(z)=h ₀ 1+a ₁ z ^-1 +a ₂ z ^-2 /1−b ₁ z ^-1 +b ₂ z ^-2 , where z=γej〓, ω=2π/ _S ,
_S is the sampling frequency. Then, as mentioned above, if we choose the frequency _O around the pole frequency, ω = 2π _O / _S. However, the form of the transfer function H(z) cannot be easily handled as described above.

The present invention changes the sampling frequency _S to the center frequency _O
The above equation is processed as 4 times . By doing this, ω=2π _O / (4 _O )=
π/2, z ^-1 = γe ^-j 〓=-γj, z ^-2 = γe ^-2j 〓=-γ. As mentioned above, since the weekly wave number of the pole is selected as the center frequency, when these values of z ^-1 and z ^-2 are put in the denominator, 1+γjb ₁ +γb ₂ =0. From this formula, b ₁ = 0, b ₂ = -1,
In reality, the value of the denominator oscillates, so it is expressed as b ₂ =-1+2 ^-n, slightly separated from b ₂ =-1.
In other words, a small bit shift value is sufficient. On the other hand, if we set zero points at two points, frequency 0 and _S /2 (2 _O ), and set a ₁ = 0 and a ₂ = -1, the transfer function H(z) at this time is H(z) = 2 ^{- n -1} 1-z ^-2 /1+(1-2 ^-n )z ^-2 .

The configuration of the digital filter 33 directly realizes the above transfer function, and the denominator -1+
The calculation of 2 _-o is performed by a circuit in which the bit inversion 34 and the n-bit right shift 35 are provided in parallel, the calculation of -1 in the numerator is performed by the bit inversion 36, and the calculation of 2 ^-n-1 is performed by the n-bit right shift 37. This is done by shifting 38 to the right by 1 bit. Delay devices 39 and 40 are exactly the same as delay devices 20 and 21 in FIG. 3, and both have a sampling period of 1/ _S as their delay amount. There is no need to particularly explain the adders 41, 42, and 43.

As can be seen from the above description, the digital tank circuit according to the present invention shown in FIG. 1 can operate completely as the conventional circuit shown in FIG. 3 without using a multiplier with a complicated configuration.

FIG. 2 is a diagram showing the configuration of a second embodiment of the present invention. This circuit differs from the circuit shown in FIG.
and delay devices 45 and 4 including this adder.
6. A quantization error canceling circuit 49 consisting of a bit inverter 47 and a lower n bit cutout 48 for shifting the signal to the left by n bits is provided. In this additional circuit, if the amount cut off (quantization error) during the operation of the n-bit right shift 35 is e(t), the output of the lower n bit cut-out 48 is 2 ⁿ e( t), and the inverted quantity -2 ⁿ e(t) of this quantity is applied to the adder 44 through two stages of delay circuits 46 and 45, and fed back. At this time, when considering e(t) as an input, the transfer function He(z) from the output point of the n-bit right shift 35 to the output point of the 1-bit right shift 38 is He(z)=2 ^-1 (1+z ^-2 ) (1-z ^-2 )/1+(1-2 ^-n
)z ^-2 , in this formula z=γej〓, j ² = −1
|He when changing ω from 0 to 2π
The maximum value of (z)| is ‖He‖ _∞ ≡ max |z|=1|He(z)|≒1, assuming that its norm is ∞. That is, the error e(t) in the output of the n-bit right shifter 35 is not amplified. In other words, since the amplitude of e(t) is at most Δ/2 (Δ=2 ^{- b} , b is the number of bits after the decimal point), the amplitude of the error component in the output is Δ/2.
It will be about 2.

On the other hand, when no additional circuit is provided, if He′(z) is the transfer function when e _t is considered as an input, ‖He′(z)‖∞≡ max ｜z｜=1｜He(z)｜=2 ⁿ , the error in the output of the n-bit right shift 35 is amplified by a maximum of 2 ⁿ times, and the amplitude of the error component in the output is 2 ⁿ
It becomes about Δ/2. That is, if there is no additional circuit, the lower n+1 bits of the output will contain an error, but with the additional circuit, the error will be suppressed to only the lower 1 bit and the error will be canceled out.

As can be seen from the above explanation, by providing this additional circuit, the quantization error component is largely canceled out. Therefore, the digital tank circuit shown in FIG. 3 has extremely excellent characteristics as a tank circuit, since the circuit configuration is simplified by not using a multiplier.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention,
FIG. 2 is a diagram showing the configuration of a second embodiment of the present invention,
FIG. 3 is a diagram showing a conventional digital tank circuit configuration. Explanation of symbols: 14, 15, 16, 17 are multipliers, 20, 21 are delayers, 31 is comparator, 32 is sampler, 33 is digital filter, 34 is bit inversion, 35 is n-bit right shift, 36 is 37 is n-bit right shift, 38 is 1-bit right shift, 39 and 40 are delay circuits (combined as delay means), 45 and 46 are delay circuits (combined as additional delay means), 47 is bit inversion, 48 49 represents a quantization error canceling circuit.

Claims (1)

[Scope of Claims] 1. The above-mentioned _{2 .} Center frequency from base code
In a tank circuit consisting of a digital filter that extracts the timing of _O , the sampling frequency _S is selected to be four times the center frequency _O ,
and first and second adders in which the digital filter is arranged in the same direction in series, where n is a positive integer, and whose intermediate point is connected to the input of the delay means, and the output is connected to the first adder. a third adder connected to one input of the adder, an n-bit right shift which receives the binary code and sends its output to the other input of the first adder, and a common output of the delay means; a bit inverter and n-bit right shift parallel circuit that receives the output of the delay means and sends the output to two inputs of the third adder, respectively; a bit inverter that receives the output of the delay means and sends the output to the second adder; , said second
1. A digital tank circuit comprising: receiving the output of the adder and shifting the output by one bit to the right to obtain the timing signal having the center frequency _O. 2 converting the analog signal into a binary code sampled at a frequency _S , and using a delay means whose delay time corresponds to two cycles of the sampling frequency, 1/ _S , to convert the binary code to the center frequency.
In a tank circuit consisting of a digital filter that extracts the timing of _O , the sampling frequency _S is selected to be four times the center frequency _O ,
and first and second adders in which the digital filter is arranged in the same direction in series, where n is a positive integer, and whose intermediate point is connected to the input of the delay means, and the output is connected to the first adder. a third adder connected to one input of the first adder; Bit inversion for sending the output to one input of the third adder, and n-bit right shifting for receiving the output of the delay means through a fourth adder and sending the output to the other input of the third adder. a parallel circuit that takes the output of the fourth adder as an input, extracts the lower n bits, inverts the bits, and has substantially the same delay time as the delay means, and outputs the output to the input of the fourth adder. a series circuit having additional delay means arranged in the stated order; a bit inverter that receives the output of the delay means and sends the output to the second adder; and a bit inverter that receives the output of the second adder and outputs the output at the center frequency. A digital tank circuit characterized in that it has a 1-bit right shift to obtain a timing signal of _O.