JPH03145186A - Semiconductor module - Google Patents

Semiconductor module

Info

Publication number
JPH03145186A
JPH03145186A JP1283351A JP28335189A JPH03145186A JP H03145186 A JPH03145186 A JP H03145186A JP 1283351 A JP1283351 A JP 1283351A JP 28335189 A JP28335189 A JP 28335189A JP H03145186 A JPH03145186 A JP H03145186A
Authority
JP
Japan
Prior art keywords
printed circuit
circuit board
board
semiconductor
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1283351A
Other languages
Japanese (ja)
Inventor
Tetsuro Tsuji
哲朗 辻
Hitoshi Toda
均 戸田
Tsugio Tawara
田原　次夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1283351A priority Critical patent/JPH03145186A/en
Priority to GB9023214A priority patent/GB2237691B/en
Publication of JPH03145186A publication Critical patent/JPH03145186A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/50—Fixed connections
    • H01R12/51—Fixed connections for rigid printed circuits or like structures
    • H01R12/55—Fixed connections for rigid printed circuits or like structures characterised by the terminals
    • H01R12/57—Fixed connections for rigid printed circuits or like structures characterised by the terminals surface mounting terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10386—Clip leads; Terminals gripping the edge of a substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ボードに表面実装される半導体モジュール
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor module that is surface mounted on a board.

〔従来の技術〕[Conventional technology]

従来、半導体集積回路等の半導体素子をプリント基板の
ボードに実装する場合、第５図に示すように、ボード１
の所定個所に多数の挿通孔２が形成され、複数個の半導
体素子３のリード４が、それぞれ対応する挿通孔２に挿
通され、各半導体素子３のリード４の先端が、配線パタ
ーンが形成されたボード１の裏面側に導出され、導出さ
れた各リード４の先端部分がフローソルダリング法等の
半田付は方法によりボード１の配線パターンに接続され
、複数個の半導体素子３のボード１への実装が行われて
いる。Conventionally, when mounting a semiconductor element such as a semiconductor integrated circuit on a printed circuit board, a board 1 is mounted as shown in FIG.
A large number of insertion holes 2 are formed at predetermined locations, the leads 4 of a plurality of semiconductor elements 3 are inserted into the corresponding insertion holes 2, and a wiring pattern is formed at the tip of the lead 4 of each semiconductor element 3. The tip of each lead 4 is connected to the wiring pattern of the board 1 by soldering such as flow soldering, and then connected to the board 1 of the plurality of semiconductor elements 3. is being implemented.

このとき、各半導体素子３が、例えばメモリＩＣなどの
同種類のＩＣばかりで、これらのＩＣ間の相互接続が極
めて単純なものであっても、ボード１への実装は挿通孔
２へのリード４の挿入により行っている。At this time, even if the semiconductor elements 3 are all of the same type, such as memory ICs, and the interconnection between these ICs is extremely simple, mounting on the board 1 involves connecting the leads to the insertion holes 2. This is done by inserting 4.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体素子３のボード１への実装は以上説明した
ように、挿通孔２へのリード４の挿入により行っている
ため、実装面積が非常に大きく、高さも高くなり、メモ
リボードのように同種類の半導体素子を集約する必要が
ある場合に、各素子間の配線が極めて単純なケースでも
、実装面積及び高さが高くなり、この種のボード１を機
器に装備した際に、機器の小型化を図る上で大きな支障
になるという問題点があった。As explained above, the conventional mounting of the semiconductor element 3 on the board 1 is carried out by inserting the leads 4 into the insertion holes 2, so the mounting area is very large and the height is also high, making it difficult to mount the semiconductor element 3 on the board 1 like a memory board. When it is necessary to consolidate the same type of semiconductor elements, even if the wiring between each element is extremely simple, the mounting area and height will be high, and when this type of board 1 is installed in the equipment, There was a problem in that it was a major hindrance to miniaturization.

この発明は、上記のような問題点を解決するためになさ
れたもので、複数個の半導体素子を表面実装用にモジュ
ール化し、実装面積及び高さの低減を図り、高密度実装
を可能にすることを目的とする。This invention was made to solve the above-mentioned problems, and makes it possible to modularize a plurality of semiconductor elements for surface mounting, reduce the mounting area and height, and enable high-density mounting. The purpose is to

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体モジュールは、所定の配線パター
ンが形成された表面実装用のプリント基板と、前記配線
パターンに接続されて前記プリント基板に搭載された複
数個の半導体素子と、前記プリント基板の周端部に装着
され前記配線パターンを介して前記各半導体素子に接続
されたクリップリードフレームとを備えたことを特徴と
している。A semiconductor module according to the present invention includes a printed circuit board for surface mounting on which a predetermined wiring pattern is formed, a plurality of semiconductor elements connected to the wiring pattern and mounted on the printed circuit board, and a periphery of the printed circuit board. The present invention is characterized by comprising a clip lead frame attached to an end portion and connected to each of the semiconductor elements via the wiring pattern.

〔作用〕[Effect]

この発明では、表面実装用のプリント基板の配線パター
ンに複数個の半導体素子が接続され、クリップリードフ
レームがプリント基板に装着されてモジュール化される
ため、従来のようにボードに多数の押通孔を形成する必
要がなく、表面実装用の配線基板に高密度に実装したモ
ジュールをそのままボードに接続すればよく、ボードへ
の高密度実装が可能になる。In this invention, a plurality of semiconductor elements are connected to the wiring pattern of a printed circuit board for surface mounting, and a clip lead frame is attached to the printed circuit board to form a module. There is no need to form a module, and modules mounted at high density on a surface mounting wiring board can be directly connected to the board, allowing high density mounting on the board.

〔実施例〕〔Example〕

第１図（ａ）　、　（ｂ）はこの発明の半導体モジュー
ルの一字施例の平面図及び正面図である。FIGS. 1(a) and 1(b) are a plan view and a front view of a single-character embodiment of a semiconductor module of the present invention.

第１図（ａ）　、　（ｂ）を参照して、表面実装用のプ
リント基板５の表、裏の両面には、素子相互間の配線用
及び素子、クリップリードフレーム間の配線用の所定の
配線パターンが形成され、この配線パターンに所定量の
半田ペーストが印刷され、プリント基板５の両面に印刷
された半田ペーストに複数個のメモリＩＣからなる半導
体素子６が仮付けされ、リフローソルダリング法等の半
田付は方法により半田付けされ接続されたのち、プリン
ト基板５の左、右の両端部に、第２図（ａ）　、　（ｂ
）に示すようなりリップリードフレーム７のクリップ部
分７ａが装着され、クリップリードフレーム７のリード
部分７ｂが適当な長さになる位置で切断されてタイバ一
部分７Ｃが除去され、半田デイツプ法等の半田付は方法
により、第３図（ａ）　、　（ｂ）に示すように、クリ
ップリードフレーム７のクリップ部分７ａとプリント基
板５の両面のクリップリードフレーム接続用の半田ペー
ストＰとが半田付けされてモジュール化され、複数個の
メモリＩＣからなる半導体モジュールが形成される。Referring to FIGS. 1(a) and 1(b), on both the front and back sides of the printed circuit board 5 for surface mounting, there are predetermined wires for wiring between elements and between elements and clip lead frames. A wiring pattern is formed, a predetermined amount of solder paste is printed on this wiring pattern, and a semiconductor element 6 consisting of a plurality of memory ICs is temporarily attached to the solder paste printed on both sides of the printed circuit board 5 using a reflow soldering method. After soldering and connecting according to the method shown in FIGS. 2(a) and (b),
), the clip portion 7a of the lip lead frame 7 is attached, the lead portion 7b of the clip lead frame 7 is cut at an appropriate length, the tie bar portion 7C is removed, and soldering is performed using a solder dip method or the like. Depending on the attachment method, as shown in FIGS. 3(a) and 3(b), the clip portion 7a of the clip lead frame 7 and the solder paste P for connecting the clip lead frame on both sides of the printed circuit board 5 are soldered. The semiconductor module is modularized and includes a plurality of memory ICs.

そして、プリント基板等のボードに前記した半導体モジ
ュールを接続する場合、第４図に示すように、ボード８
に形成された所定の配線パターン上にクリップリードフ
レーム７のリード部分７ｂが当接されて半導体モジュー
ルが配設されたのち、クリップリードフレーム７の各リ
ード部分７ｂとボード８の配線パターンとが半田付けさ
れ、ボード８に半導体モジュールが接続される。When connecting the semiconductor module described above to a board such as a printed circuit board, as shown in FIG.
After the lead portions 7b of the clip lead frame 7 are brought into contact with the predetermined wiring patterns formed on the board 8 and the semiconductor module is disposed, each lead portion 7b of the clip lead frame 7 and the wiring pattern of the board 8 are soldered. and the semiconductor module is connected to the board 8.

このように、プリント基板５の両面の配線パターンに複
数個の半導体素子６を接続し、クリップリードフレーム
７を装着し、配線パターンを介してクリップドフレーム
７と各素子６とを接続してモジュール化したため、従来
のように、複数個の同種類の半導体素子を実装する場合
でもボード８に多数の挿通孔を形成する必要がなく、従
来よりも実装面積及び高さを大幅に低減でき、ボード８
を機器に装備した場合に機器の小型化を図ることができ
る。In this way, a plurality of semiconductor elements 6 are connected to the wiring patterns on both sides of the printed circuit board 5, a clip lead frame 7 is attached, and the clipped frame 7 and each element 6 are connected via the wiring patterns to form a module. Because of this, there is no need to form many insertion holes in the board 8 even when mounting multiple semiconductor elements of the same type as in the past, and the mounting area and height can be significantly reduced compared to the past. 8
When equipment is equipped with this, it is possible to downsize the equipment.

なお、プリント基板５として、前記したポリイミド樹脂
以外に、セラミックやその他の材質のものを用いてもよ
いのは勿論である。Note that, of course, the printed circuit board 5 may be made of ceramic or other materials other than the above-mentioned polyimide resin.

また、上記実施例では、半導体素子をメモリＩＣとした
場合について説明したが、半導体素子は特にこれに限る
ものではなく、パワーデバイス等の他の半導体素子であ
っても、この発明を同様に実施することができる。Further, in the above embodiments, a case has been described in which the semiconductor element is a memory IC, but the semiconductor element is not particularly limited to this, and the present invention can be similarly implemented in other semiconductor elements such as power devices. can do.

さらに、異なる種類の半導体素子を表面実装する場合に
もこの発明を適用することができ、このときプリント基
板５の配線パターンは各素子間の配線に応じて複雑にな
る。Furthermore, the present invention can be applied to the case where different types of semiconductor elements are surface mounted, and in this case, the wiring pattern of the printed circuit board 5 becomes complicated depending on the wiring between each element.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、プリント基板の配線
パターンに複数個の半導体素子を接続して各素子をプリ
ント基板に搭載し、プリント基板にクリップリードフレ
ームを装着し、配線パターンを介してクリップリードフ
レームと半導体素子を接続したため、従来に比べて実装
面積、高さを大幅に低減することができ、特にメモリモ
ジュールのように、同種類の、Ｉ　Ｃなどを集約して実
装する場合に極めて有効であり、機器に装備した場合に
機器の小型化を図ることが可能となり、実装密度が高く
、かつ取扱いの容易な半導体モジュールを提供すること
ができる。As described above, according to the present invention, a plurality of semiconductor elements are connected to the wiring pattern of a printed circuit board, each element is mounted on the printed circuit board, a clip lead frame is attached to the printed circuit board, and a plurality of semiconductor elements are connected to the wiring pattern of the printed circuit board. By connecting the clip lead frame and the semiconductor element, the mounting area and height can be significantly reduced compared to conventional methods, especially when mounting ICs of the same type such as memory modules. This is extremely effective, and when installed in equipment, it becomes possible to reduce the size of the equipment, and it is possible to provide a semiconductor module that has a high packaging density and is easy to handle.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）　、　（ｂ）はこの発明の半導体モジュー
ルの一実施例の平面図及び正面図、第２図（ａ）　、　
（ｂ）は第１図のクリップリードフレームの正面図及び
右側面図、第３図（ａ）　、（ｂ）は第１図のプリント
基板の一部の平面図及びクリップリードフレームを接続
した状態の一部の平面図、第４図は第１図の半導体モジ
ュールをボードに接続した状態の正面図、第５図は従来
の半導体素子の実装状態を示す正面図である。 図において、５はプリント基板、６は半導体素子、７は
クリップリードフレームである。 なお、各図中同一符号は同一または相当部分を示す。FIGS. 1(a) and 1(b) are a plan view and a front view of an embodiment of the semiconductor module of the present invention, and FIG. 2(a),
(b) is a front view and right side view of the clip lead frame in Figure 1, and Figures 3 (a) and (b) are a plan view of a part of the printed circuit board in Figure 1 and the state in which the clip lead frame is connected. FIG. 4 is a front view of the semiconductor module shown in FIG. 1 connected to a board, and FIG. 5 is a front view showing a state in which a conventional semiconductor element is mounted. In the figure, 5 is a printed circuit board, 6 is a semiconductor element, and 7 is a clip lead frame. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] （１）　所定の配線パターンが形成された表面実装用の
プリント基板と、前記配線パターンに接続されて前記プ
リント基板に搭載された複数個の半導体素子と、前記プ
リント基板の周端部に装着され前記配線パターンを介し
て前記各半導体素子に接続されたクリップリードフレー
ムとを備えたことを特徴とする半導体モジュール。(1) A printed circuit board for surface mounting on which a predetermined wiring pattern is formed, a plurality of semiconductor elements connected to the wiring pattern and mounted on the printed circuit board, and a plurality of semiconductor elements mounted on the peripheral edge of the printed circuit board. A semiconductor module comprising: a clip lead frame connected to each of the semiconductor elements via the wiring pattern.
JP1283351A 1989-10-30 1989-10-30 Semiconductor module Pending JPH03145186A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1283351A JPH03145186A (en) 1989-10-30 1989-10-30 Semiconductor module
GB9023214A GB2237691B (en) 1989-10-30 1990-10-25 Electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1283351A JPH03145186A (en) 1989-10-30 1989-10-30 Semiconductor module

Publications (1)

Publication Number Publication Date
JPH03145186A true JPH03145186A (en) 1991-06-20

Family

ID=17664359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1283351A Pending JPH03145186A (en) 1989-10-30 1989-10-30 Semiconductor module

Country Status (2)

Country Link
JP (1) JPH03145186A (en)
GB (1) GB2237691B (en)

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GB9023214D0 (en) 1990-12-05
GB2237691A (en) 1991-05-08
GB2237691B (en) 1993-08-25

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