JPH03150836A - Charged beam lithography method - Google Patents

Abstract

PURPOSE:To accelerate data conversion process by assigning an ICPU for each frame region and each chip, and processing the data conversion of entire mask data by a plurality of CPUs in parallel. CONSTITUTION:Independent data systems are provided for LSI subchips 51-55 for forming a lithography mask 50. Design pattern data regarding the LSI subchips are formed of several block regions 2, 3, 5, 6, 9 of the entire region 1 of LSI chip and several graphic patterns 1A-1D. When lithography data are generated, each frame of lithography unit region of a plurality of LSI chips and LSI chip regions for forming the mask is processed by an ICPU, and processed in parallel at frame unit and chip unit. Thus, data conversion time can be accelerated.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is directed to a charging method for drawing patterns of semiconductor integrated circuits such as LSIs on samples such as masks and semiconductor wafers at high speed and with high precision. The present invention relates to a beam lithography method, and particularly to a charged beam lithography method that enables high-speed generation of lithography pattern data acceptable to an apparatus.

(Prior Art) In recent years, LSI patterns have become increasingly finer and more complex, and electron beam lithography devices are widely used as devices for forming such patterns. When drawing a desired pattern using this device, LS such as CAD
Design pattern data created using the pattern design tool I cannot be supplied as drawing pattern data to the above-mentioned drawing apparatus in its original format. In other words, the data system defined by the design pattern data is generally created as a data system with a very high degree of freedom, so in order to make the data system acceptable to the electron beam lithography system, the following is required. must satisfy certain restrictions.

■ Defined as a figure system consisting only of basic figures (trapezoids, rectangles, etc.) that can be accepted by electron beam lithography equipment.

■ Must be defined using a data system that does not allow overlapping figures, which would result in multiple exposures and reduce pattern formation accuracy.

■ Defined in a data system divided into predetermined unit lithography areas according to the lithography method of the electron beam lithography system.

Therefore, the multiple exposure area is removed using a method such as contouring processing from the above design pattern data, and then a unique unit drawing area (
By dividing the graphics into basic graphic groups such as rectangles, trapezoids, and triangles for each frame area and subfield area, a graphic data system acceptable to the electron beam lithography apparatus is created. Then, drawing pattern data related to a desired LSI chip is generated based on data of such a graphic system, and the drawing pattern data is stored in a storage medium typified by a magnetic disk and used for drawing.

Then, in the drawing processing step, the above drawing pattern data is
Each drawing stripe area (an area where frame areas are collected according to a predetermined rule), which is a unit area that can be drawn by continuous movement of the table, is read out and temporally stored in the pattern memory section. The data stored in this pattern memory is decoded and a desired pattern is constructed from a collection of drawing unit figures (rectangles with limits on figure size and triangles with limits on shape and size) that can be formed by beam shaping means. The beam position and beam shape are controlled based on the resulting graphic data, and the table on which the sample is placed is continuously moved in the X or Y direction to draw stripes. Draw the desired pattern within the area.

Next, the table is moved in steps by the width of the drawing stripe area in a direction perpendicular to the continuous movement direction, and the above process is repeated to perform the drawing process on the entire desired area. In addition, in a two-stage deflection method in which the main deflection means controls the sub-deflection position and the sub-deflection means draws a desired pattern in the sub-deflection area, the frame area is composed of a collection of unit drawing areas (sub-fields). A collection of these frame areas constitutes a drawing stripe area, and the width of the drawing stripe is defined by the beam deflection width of the main deflection means and the sub-deflection means.

As mentioned above, when generating the drawing pattern data to be used in the drawing process, as a countermeasure for the miniaturization and high integration of LSI patterns, it is necessary to The drawing pattern data was compressed by composing the drawing pattern data with a group of graphic patterns and their repetition information. The reason for this is that in data conversion processing for memory devices, where pattern density is becoming finer and integration density is increasing rapidly, computer resources will be severely strained unless data compression using the above-mentioned repeating structure is performed. This is because data conversion is no longer possible because it takes a long time and becomes impractical.

On the other hand, the mask pattern drawn through the above-mentioned process is usually inspected by a defect inspection device to verify whether the formed pattern is formed according to the design pattern data or not, and whether there are any pattern defects. A pattern inspection is carried out by the method, and only masks that pass a predetermined standard and masks that have been modified based on the inspection results are used as pattern transfer masks to the wafer.

Normally, the input data to the above-mentioned drawing equipment and defect inspection equipment is either converted into pattern data that can be required by each equipment based on design pattern data, or generated as data for drawing or inspection. The data is stored in advance, and the data is converted as necessary at the time of drawing or inspection, and then subjected to a processing step of being used for drawing or inspection.

A computer system that also serves as a drawing device or an inspection device is generally used for such various data conversion processes, and as mentioned above, the data conversion unit processes one drawing mask data sequentially into drawing pattern data using one CPU. The processing method used was to convert the data into .

However, this type of method has the following problems. In other words, the time required to create drawing pattern data (data conversion) for one LSI chip is limited by the processing performance of the CPU. In the data processing process, there are many situations in which the CPU becomes idle when inputting and outputting data to and from the disk, resulting in wasted processing.

Due to this situation, in the current data conversion process,
There is a limit to the ability to quickly generate desired drawing pattern data from design pattern data created with CAD or drawing pattern data for defect inspection or using different drawing methods, and as LSIs continue to become smaller and more highly integrated. This leads to a longer data conversion time, and as the drawing throughput of the drawing apparatus itself improves, the supply of drawing pattern data cannot keep up. In other words, it is quite possible that the data conversion process will limit the drawing throughput, and there will always be calls for computer expansion and performance improvement.

These problems will reduce the operation rate of electron beam lithography equipment and cause a decline in LSI productivity.In the future, with the rapid progress of LSI, pattern miniaturization and increased integration will lead to electronic This poses a major problem in increasing the reliability of the LSI pattern written by the beam drawing device and the operating rate of the device.

(Problem to be Solved by the Invention) Conventionally, in the process of converting drawing pattern data from design pattern data, etc., it has been possible to convert drawing pattern data to one drawing mask without considering the application of a parallel computer equipped with multiple CPUs. Data conversion processing is performed using a processing procedure in which related drawing pattern data is sequentially subjected to drawing processing by one CPU. As a result, the data conversion processing time (the time from when design pattern data is actually input until the drawing pattern data is output) becomes longer, which is likely to lead to a decrease in drawing throughput. Conceivable.

Furthermore, it is estimated that the data conversion time will be limited to the above-mentioned data conversion time when drawing a mask with a very short lead time. Note that the above-mentioned problem is not limited to the electron beam drawing method, but also applies to the ion beam drawing method using an ion beam and the laser drawing method using a laser.

The present invention has been made in consideration of the above circumstances, and its purpose is to prevent data creation time from being limited by the processing performance of the CPU when generating drawing pattern data from design pattern data. Another object of the present invention is to provide a charged beam lithography method that can speed up data conversion processing, shorten data conversion time, and improve lithography throughput.

[Structure of the Invention] (Means for Solving the Problem) The gist of the present invention is to
By allocating one CPU to each frame area, which is the unit drawing area of the SI chip, and to each chip, data conversion processing of the entire mask data is processed in parallel by multiple CPUs.
The objective is to convert drawing pattern data necessary for one drawing mask at high speed.

That is, the present invention divides a drawing area, which is a collection of LSI chips placed on a sample, into drawing stripe areas of a predetermined width, reads out drawing pattern data from a storage medium for each drawing stripe area, and then places the sample on the sample. In a charged beam drawing method in which a desired pattern is drawn while a table is continuously moved in one direction, when generating drawing pattern data to be stored in the storage medium in advance, drawing pattern data (hereinafter referred to as stripe data) for each drawing stripe area is generated. ) that constitutes the LS! The drawing pattern data for each chip (hereinafter referred to as chip data) defines the drawing pattern data for each frame area divided by the predetermined width (hereinafter referred to as frame data), and the frame data is generated. In this case, a plurality of CPUs process frame data of a plurality of frames in parallel.

Further, in the present invention, when generating the chip data, the chip data is generated by parallel processing of frame data that is more than the number of CPUs installed in the computer that processes the data, and a drawing area to be processed for drawing on the sample. In this method, when generating drawing pattern data in which a plurality of types of LSI chips are arranged, the plurality of types of chip data are processed in parallel by a plurality of CPUs for data conversion.

(Function) According to the method of the present invention, when generating drawing pattern data related to a drawing mask composed of at least one LSI chip, a plurality of LSI chips constituting the drawing mask are
Processing is performed by the CPU for each frame area, which is a drawing unit area of the chip and the LSI chip area, and parallel processing is performed on a frame-by-frame and chip-by-chip basis, making it possible to significantly speed up data conversion time. .

Therefore, it is possible to significantly shorten the processing time for converting the drawing pattern data required for one drawing mask, and as a result, it is possible to increase the operating rate of the charged beam drawing apparatus and to improve the productivity of LSI. Also,
The data conversion method of the charged beam lithography system is expected to be more effective in the future as patterns become smaller and more highly integrated, and there is a demand for shorter delivery times for lithography masks.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a schematic diagram showing the configuration of an electron beam lithography system used in a method according to an embodiment of the present invention.

In the figure, reference numeral 10 denotes a sample chamber, and a table 12 on which a sample 11 such as a glass mask or a semiconductor urchin is placed is accommodated in the sample chamber 10. The table 12 is driven by a table drive circuit 13 in the X direction (left and right directions on the paper) and the Y direction (front and back directions on the paper). And table 12
The movement position is determined by a position circuit 14 using a laser nJ length meter, etc.
It is measured by

An electron beam optical system 20 is arranged above the sample chamber 10. This optical system 20 includes an electron gun 21, various lenses 2
2-26, blanking deflector 31. Beam dimension variable deflector 32. Main deflector 33 for beam scanning. Sub deflector 34 for beam scanning and beam shaping aperture 85.3
It is composed of 6th grade. Then, it is positioned in a predetermined unit drawing area (subfield) by the main deflector 33,
The sub-deflector 34 positions the figure drawing position within the sub-field, and the beam dimension variable deflector 32
The beam shape is controlled by the shaping apertures 35 and 36, and while the table 12 is continuously moved in one direction, the LSI chip pattern area is drawn in a drawing stripe area that is collected within the range that can be drawn by one continuous movement of the table. . In other words, a drawing stripe area, which is a collection of frame areas obtained by dividing the LSI chip pattern area into strips according to the deflection width of the beam, is subjected to writing processing. Furthermore, table 12
is moved stepwise in a direction perpendicular to the direction of continuous movement, and the above process is repeated to sequentially draw each drawing stripe area.

On the other hand, the control computer 40 has a magnetic disk (storage medium) 4.
1 is connected, and the drawing pattern data of the LSI chip is stored in this disk 41. The drawing pattern data of the LSI chip read from the magnetic disk 41 is temporarily stored in a pattern memory (data buffer section) 42 for each drawing stripe area.

The drawing pattern data for each drawing stripe stored in the pattern memory 42, that is, the drawing stripe information composed of drawing positions, basic figure data, etc., is decoded by a pattern data decoder 43 and a drawing data decoder 44, which are data decoding units. It is sent to a blanking circuit 45 , a beamformer driver 46 , a main deflector driver 47 and a sub-deflector driver 48 .

That is, the pattern data decoder 43 inputs the drawing pattern data for each drawing stripe area, expands the compressed drawing figure data based on the pattern repetition information defined as the drawing stripe data, and
In the drawing process of the drawing stripe area, the drawing figure data defined in the drawing pattern data is transferred to the forming forming aperture 35 while determining and decoding for each subfield whether or not it is an area to be drawn and the area to be drawn next. The beam control data is created based on this data and sent to the blanking circuit 45.

Then, the desired beam dimension data is created,
Control data for this beamforming is sent to beamformer driver 46. Next, the beamformer driver 46
A predetermined deflection signal is applied to the beam size variable deflector 32 of the optical system 20, thereby controlling the size of the electron beam.

Further, the drawing data decoder 44 decodes and creates subfield positioning data based on the drawing stripe data, and sends it to the main deflector driver 47. Then, a predetermined signal is applied from the main deflector driver 47 to the main deflector 33 of the optical system 20, whereby the electron beam is deflected and scanned to a designated subfield position.

Further, the drawing data decoder 44 generates a control signal for scanning the sub-deflector, and this signal is sent to the sub-deflector driver 48. Then, a predetermined sub-deflection signal is applied from the sub-deflector driver 48 to the sub-deflector 34, thereby performing drawing processing for each sub-field. The beam drawing method will be explained. FIG. 2 shows the process of generating data for performing the drawing process. LSI patterns are designed and created (digitized) using a CAD system, and the design pattern data is device-specific depending on the lithography method of the electron beam lithography system using a host computer with high processing power, including a large computer. The data is converted into a drawing pattern.

Based on this drawing pattern data, the positioning and beam shape of the electron beam are controlled to perform a series of drawing processes.

Here, the data created by the CAD system is
As shown in Figure (a), the LSI that constitutes the drawing mask 50
Each subchip 51 to 55 has an independent data system, and the design pattern data related to each LSI subchip is divided into several block areas (2 ,3,5゜6.
9) and several graphic patterns IA to ID, and its reference block 2 is constructed by repeating block areas 4 as shown in FIG. 3(e). Furthermore, the reference block 3 is composed of block areas 7 and 8 and a graphic pattern 3A as shown in FIG. 3(d), and the entire LSI chip is expressed by a combination of multiple block areas and graphic patterns. The data system is based on

Note that although block areas 5, 6, and 9 are not particularly illustrated, they will be described below as block areas that are composed only of graphic patterns without reference to block areas.

As shown in FIG. 4, the design pattern data representing each block area is composed of a block reference information group and a graphic data group defining a graphic pattern. The design pattern data shown in Fig. 4 is
This relates to block area 1 of the entire LSI chip shown in FIG. 2B, and the graphic pattern included in each block area is data-defined as a polygonal pattern. Furthermore, these figures have a system that allows patterns to overlap with each other. Furthermore, there are no particular restrictions on the overlap between block areas.

In order to convert LSI pattern data in this format into a graphic data system that can be accepted by an electron beam lithography system, the host computer performs preprocessing (for example, 82-327
No. 19).

Furthermore, the block references of the LSI chip are terminated to block 1, which represents the entire chip area, and the design pattern data is Perform reorganization processing. That is, an expansion process is performed to limit the block reference relationship to the level, and a data system is created such that the block reference relationship is as shown in FIG.

Then, for the graphic pattern group included in each block area, mutual overlap removal processing is performed using methods such as the slit method and the touch jig method, and a process is performed to eliminate multiple exposure areas of drawn figures. Perform graphic processing. Next, as shown in FIG. 6, the entire area 1 of the LSI chip is
is divided into temporary frame regions (61 to 66) determined by the main deflection width of the beam.

In FIG. 6, the table continuous movement direction is in the left-right direction on the paper, and the table step movement direction is in the vertical direction on the paper.

When constructing the frame data of the frame areas 61 to 66, a plurality of CPUs are used to perform data conversion processing. Specifically, data conversion processing for the first frame area 61 is performed by the first CPU, data conversion processing for the second frame area 62 is performed by the second CPU, and data conversion processing for the n-th frame area is performed by the n-th CPU.
Processed in PU. In data processing on the CPU, in order to efficiently use the CPU free space created during data input/output processing, data conversion processing for at least two frame areas is processed by time sharing as shown in Figure 7. ing.

Next, the data conversion process performed for each frame process will be explained. The above provisionally divided frame area 61
~66 (hereinafter referred to as a virtual frame area), the drawing position of the block area is defined by the relative position from the reference position of the virtual frame area, and is composed of position data and array attribute information. A collection of block drawing data consisting of block arrangement data and block figure data as shown in FIG. 8, which is grouped into subfield areas in which figures to be drawn in the block area can be deflected by the sub-deflection means. Generate frame data as

The frame data group obtained in this way is stored on the magnetic disk 4.
It is stored in 1. Further, parallel processing using multiple CPUs as described above is not limited to frame processing of one LSI chip, but also processing of frames of LSI subchip 5 arranged in the mask 50.
1 to 55 is also used to speed up processing. Based on the drawing pattern data stored in the magnetic disk 41, for example, "Patent Application No. 1-15018
By performing the drawing process using the method disclosed in No. 8'', it is possible to achieve high-speed and highly accurate drawing processing.

Thus, according to the method of this embodiment, design pattern data created by a CAD system can be converted into highly consistent drawing pattern data at high speed. That is, C
When generating drawing pattern data necessary to draw a desired pattern from design pattern data designed and created by an AD system, data conversion processing for each frame area, which is a unit drawing area, is processed by multiple CPUs. As a result, extremely efficient data conversion processing can be realized, and data conversion time can be significantly speeded up. As a result, the operating rate of the drawing device itself can be increased,
It can contribute to improving LSI productivity.

In addition, as another example, writing pattern data (hereinafter referred to as conventional data) is used as it is as reference data for the reticle defect inspection system, and in order to ensure consistency with the reticle defect inspection system, the above-mentioned writing pattern data is converted into writing pattern data using a two-stage deflection method. There is a need. In that case, since the beam deflection width of the frame area of the one-stage deflection method described above is extremely narrow compared to the frame area of the two-stage deflection method, data for n frames of conventional data are usually collected to create a new one.
Generate frame data.

Specifically, one frame area of the conventional data is regarded as the one block area, and mutual overlap removal and black-and-white inversion processing are performed on the figure patterns included in the block area, and the figure pattern group is further processed into a predetermined shape. By dividing the data into subfield regions, drawing pattern data having a data structure similar to that of the frame data described above is generated.

Note that the data conversion process described above originally collects graphic patterns divided into frame areas and constructs new frame data, so the data is highly independent and the parallel processing that makes full use of multiple CPUs as described above allows for good results. It is possible to bring out the effects.

In this way, in this embodiment, by making the frame area, which is extremely independent in the data system of the electron beam lithography system, the basic unit of parallel processing, It becomes possible to significantly shorten the pattern data generation processing time, improve the operating rate of the lithography apparatus, and maximize the performance of the electron beam lithography apparatus.

Note that the present invention is not limited to the embodiments described above. For example, as a means for storing the drawing pattern data, other storage media such as a magnetic tape or a semiconductor memory can be used instead of a magnetic disk. Further, the configuration of the electron beam lithography apparatus is not limited to the same as that shown in FIG. 1, but can be modified as appropriate. In the example, explanation was given using an electron beam as an example, but the application is not limited to electron beams, but can be applied to charged beams such as ion beams and laser beams, and in addition to shot methods using variable shaped beams, elliptical beams It is also applicable to vector or rask type devices using . moreover,
The graphic system of the drawing pattern data stored in the storage medium may be not only basic figures such as rectangles and trapezoids, but also drawing unit figures and polygonal figures. Even when figures overlap, the pattern data decoder section removes the overlap between figures and inverts black and white. The present invention can be handled by adding a graphic calculation means that performs the above, and can also be applied to data of such a system, and can be implemented with various modifications without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, data conversion of the entire mask data is performed by allocating one CPU to each frame area and chip, which is a unit drawing area of an LSI chip included in the drawing area of a drawing mask. By performing processing in parallel using a plurality of CPUs, the drawing pattern data required for one drawing mask can be converted at high speed.

Therefore, when generating drawing pattern data from design pattern data, the data creation time is not limited by the processing performance of the CPU, and the data conversion process can be accelerated, reducing the data conversion time and drawing pattern data. Throughput can be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the configuration of an electron beam lithography system used in a method according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing the process of generating writing pattern data, and FIG. Figure 4 is a schematic diagram showing the data system of blocks, Figure M5 is a schematic diagram showing the block structure within the chip, Figure 6 is a schematic diagram showing virtual division into frame areas, Figure 7 FIG. 8 is a schematic diagram showing a data structure of frame data, and FIG. 9 is a schematic diagram showing a one-stage deflection drawing method. 1-9... Block, LA-ID... Figure pattern, 10... Sample chamber, 11... Sample, 12... Table, 20... Electron optical system, 21... Electron gun , 22-26...Lens, 31-34...Deflector, 35.36...Beam shaping aperture, 40...Control computer, 41...Magnetic disk (storage medium), 42... Pattern memory, 43... Pattern data decoder, 44... Drawing data decoder, 45... Blanking circuit, 46-48... Deflector driver, 51-55... LSI subchip, 61-66. ...Frame area.

Claims (7)

[Claims] (1) The drawing area, which is a collection of LSI chips arranged on the sample, is divided into drawing stripe areas of a predetermined width, and the drawing pattern data is read out from the storage medium for each drawing stripe area, and the table on which the sample is placed is read out. In a charged beam drawing method in which a desired pattern is drawn while continuously moving in one direction, when generating drawing pattern data to be stored in the storage medium in advance, stripe data corresponding to the drawing pattern data for each drawing stripe area is generated. The chip data corresponding to the drawing pattern data for each constituent LSI chip is defined as the frame data corresponding to the drawing pattern data for each frame area divided by the predetermined width, and when generating the frame data, is multiple C
A charged beam drawing method characterized by data processing multiple frames of frame data in parallel using a PU. (2) Charged beam lithography according to claim 1, characterized in that when generating the chip data, the chip data is generated by parallel processing frame data of a number greater than the number of CPUs installed in a computer processing the data. Method. (3) When generating drawing pattern data in which a plurality of types of LSI chips are arranged in a drawing area to be subjected to drawing processing on the sample, the plurality of types of chip data are transferred to a plurality of CPs.
2. The charged beam lithography method according to claim 1, wherein data processing is performed by parallel processing in U. (4) The chip data is generated from LSI chip design pattern data expressed as a set of block data composed of figure pattern data to be drawn or reference information of other blocks. 1. The charged beam drawing method according to 1. (5) The charged beam lithography method according to claim 1, wherein the chip data is generated from lithography pattern data related to charged beam lithography apparatuses using different lithography methods. (6) Charged beam lithography apparatuses with different lithography methods differ in either the predetermined width, the beam deflection method, or the beam shape control method for controlling the beam deflection means to divide the beam deflectable lithography area. The charged beam drawing method according to claim 5. (7) The drawing pattern data to be subjected to the data processing is supplied to a drawing device that performs drawing processing by deflecting and scanning a circular beam using one stage of beam deflection means, and data is generated based on the data. The beam position is controlled by a two-stage deflection system that combines a main deflection means and a sub-deflection means based on drawing pattern data, and the beam shape is controlled by a combination of two apertures to perform drawing processing. The charged beam drawing method according to item 5.