JPH03155239A - Synchronizing device - Google Patents

Abstract

PURPOSE:To attain synchronization security in a digital signal transmission system in response to the transmission state by detecting a synchronizing signal in a digital signal and controlling synchronization protection based on its detection signal and an error quantity specific signal of the digital signal. CONSTITUTION:When absence of a synchronizing signal in a digital signal is detected by a synchronization detection circuit 12, a synchronizing signal absence pulse is outputted from the circuit 12. The synchronizing signal absence pulse is counted by a synchronization protection circuit 13 and when a prescribed number of counts is consecutive, an out of synchronism pulse is outputted. Moreover, the digital signal is processed by a data processing section 14 and an error of a data processed by an error detection circuit 15 is detected and an error detection pulse is outputted. The error detection pulse is counted by an error counter 16 and an error quantity specific signal is outputted to the synchronization protection circuit 13.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a synchronization device that protects the synchronization of a digital signal composed of frame units including a synchronization signal and an error detection (correction) code. .

(Prior art) For example, in satellite broadcasting, audio signals are transmitted as digital signals, and in a system that transmits such digital signals, when transmitting a digital signal composed of frames including a synchronization signal. , a synchronization device that detects the above-mentioned synchronization signal and achieves synchronization is used.

As such a synchronizing device, there is a conventional synchronizing device as shown in FIG.

As shown in the figure, this synchronization device includes a signal input section 1 that inputs a digital signal composed of frame units including a synchronization signal and an error detection code, and a predetermined input signal in the frame unit digital signal from the signal input section 1. A synchronization detection circuit 2 detects whether a synchronization signal exists at the position of The synchronization protection circuit 3 outputs an out-of-synchronization pulse when the count continues a predetermined number of times.

By the way, in the above-mentioned conventional synchronization device used in a satellite broadcasting system, the protection range of the synchronization protection circuit 3 is fixed, so synchronization errors due to a drop in C/N (carrier-to-noise ratio), broadcast channel switching, etc. If a predetermined number of consecutive synchronization errors occur, regardless of the synchronization errors accompanying the synchronization errors, the synchronization will be lost and an out-of-synchronization pulse will be output.

This state H is shown in the state transition diagram of FIG. In the same figure,
* indicates a synchronization secured state, - dotted chain arrows indicate when there is no synchronization pattern, and solid arrows indicate when there is a synchronization pattern.

Therefore, the above-mentioned synchronization device attempts to satisfy a condition in which synchronization should be immediately removed and a condition in which synchronization should be maintained as much as possible under one condition.

(Problems to be Solved by the Invention) As mentioned above, conventional synchronization devices cannot distinguish between synchronization errors caused by C/N drop and synchronization errors caused by channel switching, and treat both in the same way. There is a problem in that it is difficult to perform processing to ensure synchronization according to the situation.

The present invention is intended to solve the above-mentioned conventional problems,
An object of the present invention is to provide a synchronization device that can ensure synchronization in a system that transmits digital signals depending on the transmission state.

[Structure of the Invention] (Means for Solving the Problems) The present invention detects whether or not the synchronization signal exists at a predetermined position of the frame from a frame-by-frame digital signal including a synchronization signal and an error detection code. a synchronization detection circuit that outputs a detection signal based on the detection result; an error detection circuit that detects an error in a data string included in the digital signal and outputs an error detection pulse when an error is detected; an error counter circuit that counts the error detection pulses from the circuit for a certain period of time, detects whether the count value is within a predetermined value range, and outputs an error amount specifying signal according to the detection result;
A synchronization protection circuit that performs synchronization protection for the digital signal, and a control circuit that inputs the detection signal and the error amount specifying signal and outputs a control signal that controls the operation of the synchronization protection circuit based on these signals. It is something that

(Function) In the present invention, since the synchronization signal in the digital signal is detected and the synchronization protection is controlled based on the detection signal which is the detection result and the error amount specifying signal which is the error amount in the digital signal, the digital signal can be It is possible to ensure synchronization in the transmission system depending on the transmission state.

(Example) Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing a synchronization device according to an embodiment of the present invention.

As shown in the figure, a digital signal composed of frames including a synchronization signal and an error detection code is input to the signal input section 11. A digital signal in units of frames from the signal input section 11 is output to a synchronization detection circuit 12, and it is detected whether or not a synchronization signal exists at a predetermined position in this digital signal. A pulse without synchronization signal is output. A pulse without a synchronization signal from the synchronization detection circuit 12 is sent to the synchronization protection circuit 13.
When the count continues for a predetermined number of times, an out-of-synchronization pulse is output. Further, the digital signal from the signal input section 11 is subjected to predetermined processing by a data processing section 14 such as a de-increment circuit, and an error detection circuit 15 detects an error in the processed data and generates an error detection pulse. is output. The error detection pulse is currented by an error counter 16, and when this count value falls within a predetermined range in a predetermined period, an error amount specifying signal is output to the above-mentioned synchronization protection circuit 13.

FIG. 2 is a diagram for explaining the above-mentioned synchronization protection circuit.

In the same figure, 21 is a frequency dividing circuit, 22 is a selector, and 23 is a frequency dividing circuit.
indicates a protection circuit that performs synchronization protection.

A pulse without a synchronization signal from the synchronization detection circuit 12 is outputted to the frequency dividing circuit 21, and a signal obtained by frequency-dividing this pulse without a synchronization signal is output. The selector 22 receives the pulse without synchronization signal frequency divided by the frequency dividing circuit 21 or the pulse without synchronization signal from the synchronization detection circuit 12, and
An error amount specifying signal from the error counter 16 is input, and a synchronizing signal-less pulse or a synchronizing signal-less pulse frequency-divided according to the error amount specifying signal is output to the protection circuit 23.

The above-mentioned error amount specifying pulse is as shown in FIG.
When the error amount in the range of error mA-B is detected in a predetermined period when the error amount at the time of channel switching is set to MAX, it becomes a pulse that becomes H (high), and the error amount other than the range of error amount A-8 mentioned above becomes a pulse. (including when switching channels), the pulse becomes L (low).

In the synchronization device configured in this manner, the synchronization detection circuit 12 detects the presence or absence of a synchronization signal at a predetermined position of the frame, and detects the presence or absence of a synchronization signal at a predetermined position of the frame. Occasionally, a pulse without a synchronization signal is generated.

These pulses are counted by the synchronization protection circuit 13, and when a predetermined number is continuously reached, the synchronization is lost.

Here, the above-mentioned digital signal is processed by a separate data processing section (
Here, the signal is processed by a de-interleaving circuit (de-interleave circuit) 14, and an error detection pulse is generated by an error detection circuit 15. This pulse is counted at an error count of 15 at regular intervals, and when the value is greater than or equal to A and less than or equal to B as shown in Figure 3,
An error amount specifying signal that becomes H is generated. This signal is L
In this case, the pulse without synchronization signal from the synchronization detection circuit 12 is directly output from the selector 22 to the protection circuit 23, and when the error amount specifying signal is H, the pulse without synchronization signal frequency-divided by the frequency dividing circuit 21 is output. Protection circuit 2 via selector 22
Output to 3.

Therefore, in this embodiment, when a synchronization signal is lost due to a drop in C/N, the error amount specifying signal becomes H, resulting in a strong (long) synchronization protection region shown by the broken line in FIG. At the time of loss, the error amount identification signal becomes L, which is weak (short) as shown by the dashed line in Figure 4.
It becomes a synchronous protection area.

[Effects of the Invention] As explained above, the synchronization device of the present invention detects a synchronization signal in a digital signal and performs synchronization protection based on the detection signal that is the detection result and the error amount identification signal that is the amount of error in the digital signal. Therefore, it is possible to ensure synchronization in a system that transmits digital signals according to the transmission state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a synchronization device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the synchronization protection circuit of FIG. 1, and FIG. 3 is a diagram for explaining an error amount specifying signal. 4 is a state transition diagram of synchronization protection operation in the device shown in FIG. 1, FIG. 5 is a block diagram for explaining a conventional synchronization device, and FIG. 6 is a diagram showing synchronization protection in the device shown in It is a state transition diagram of operation. 12... Synchronization detection circuit, 13... Synchronization protection circuit, 1
4...Data processing section, 15...Error detection circuit, 1
6... Error counter, 21... Frequency dividing circuit, 22...
... Selector, 23... Protection circuit.

Claims (1)

[Claims] Detecting whether or not the synchronization signal exists at a predetermined position of the frame from a frame-by-frame digital signal including a synchronization signal and an error detection code, and outputting a detection signal based on the detection result. a synchronization detection circuit; an error detection circuit that detects errors in a data string included in the digital signal and outputs an error detection pulse when an error is detected; and a circuit that counts the error detection pulses from the error detection circuit for a certain period of time. , an error counter circuit that detects whether the count value is within a predetermined value range and outputs an error amount specifying signal according to the detection result; a synchronization protection circuit that performs synchronization protection for the digital signal; A synchronization device comprising: a control circuit that receives a detection signal and the error amount specifying signal and outputs a control signal for controlling the operation of the synchronization protection circuit based on these signals.