JPH03162183A - Photoelectric conversion device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a photoelectric conversion device, and particularly to a photoelectric conversion device.
This article relates to a photoelectric conversion device that can be used for nine applications.

[Prior Art] Conventionally, there is a photoelectric conversion device that photoelectrically converts incident light, stores it as a signal charge, and extracts a signal corresponding to the signal charge. One such device is a charge conversion device that accumulates charge in the base region of a bibolar transistor, amplifies this accumulated charge, and extracts it from the emitter. FIG. 4 is a circuit diagram of such a conventional charging conversion device. Note that sensor circuits for four rows and four columns are illustrated here.

FIG. 5 is a timing chart for explaining the operation of the photoelectric conversion device.

In FIG. 4, l represents a sensor pixel, which is composed of a bipolar transistor Tr, a capacitor C connected to the base, and a P-type MOS transistor M.

2 is an output line connected to the emitter of the bipolar transistor Tr of the pixel, 3 is a storage capacitor for accumulating an output signal, and 4 is an MlIS to switch between the output line 2 and the storage capacitor 3. } - Range resistor 5 is a MOS for resetting the output line 2 } transistor, 6 is a horizontal output line for outputting an output signal, 7 is a horizontal output of the storage signal of the storage capacitor 3 according to the output from the horizontal shift register HSR MOS}-transistor for transferring to line 6; 8 is a MOS transistor for resetting horizontal output line 6;
9 is a horizontal drive line for driving pixels, and 10 is a buffer MOS transistor for selecting a row of pixels to be driven according to the output from the vertical shift register VSR. Vl, V2, V3, V4 are vertical shift registers VS
Output from R, PHS is the start pulse of horizontal shift register HSR, PHI, PH2 are horizontal shift register H
SR scanning pulse, upper horizontal shift register H
Outputs Hl and H3 from SR are synchronized with scanning pulse PH1, and outputs H2 and H3 from the lower horizontal shift register HSR are synchronized with scanning pulse PH1.
H4 is synchronized with scanning pulse PH2. Also, PT is MOS
The pulse applied to the gate of transistor 4, PvC is M
OS }Pulse applied to the gate of transistor 5, PR
is the drive pulse.

Below, the sensor operation will be explained according to Fig. 5.d First, when the output V1 becomes High level and the first row of sensor pixels is selected, the pulse PT is set to the old gh level, the pulse PVC is set to the LOW level, and the output The line 2 and the storage capacitor 3 are in a floating state, and the drive pulse PR is set to High.
level, and read out the pixels in the first row. Signals from pixels in odd-numbered columns are stored in the upper storage capacitor 3, and signals from pixels in even-numbered columns are stored in the lower storage capacitor 3. A signal is transferred to the upper horizontal output line 6 in synchronization with the scanning pulse PH1, and the upper horizontal output line 6 is reset in synchronization with the scanning pulse PH2. The lower horizontal output line 6 has a scanning pulse P.
A signal is transferred in synchronization with H2, and the lower horizontal output line 6 is reset in synchronization with scan pulse PH1. During this horizontal scanning, the drive pulse PR is at a LOW level, and the base of the bibolar transistor Tr of the pixel in the first row is
Becomes GND. After horizontal scanning, the drive pulse PR is }I
The base potential becomes a positive potential through capacitive coupling, and is connected to GND through transistor 5.
A forward current flows into the output line 2, which is fixed at
The base potential drops to a certain level. Drive pulse P
When R reaches the MIDDLE level, a reverse bias is created between the emitter and base of the pixel, and photoelectric charges begin to accumulate. Output Vl becomes LOW level, output v2 becomes HIGH
When the level is reached and the second row is selected, the same operation is repeated in the pixels of the second row, and in the end, the amplified signal output from the pixels is sequentially output from the upper and lower amplifiers. Become.

[Problems to be Solved by the Invention] However, in the conventional photoelectric conversion device described above, the output signal transferred to the horizontal output line 6 due to the capacitance division between the storage capacitor 3 and the horizontal output line 6 must be reset. In order to reset the horizontal output line 6, as explained in FIG. 4 and FIG. z To elevation 1) T ([1+1 Lm O L+ f Width force
1. Must. In particular, when signals for two lines must be transferred, such as in a color sensor, the signal transfer method using the conventional photoelectric conversion device described above becomes difficult. Furthermore, since the signal transfer to the horizontal output line 6 is by capacitance division,
There is a problem in that the signal voltage appearing on the horizontal output line 6 is lower than the signal voltage stored in the storage capacitor 3.

[Means for Solving the Problems] The photoelectric conversion device of the present invention electrically connects the control electrode of a Darlington type transistor to the signal output side of a photoelectric conversion element capable of accumulating photoelectrically converted charges. A load means is electrically connected to one main electrode of the transistor to form an emitter follower circuit, and a signal is read from the main electrode.

[Function] The present invention electrically connects the control electrode of a Darlington type transistor to the signal output side of a photoelectric conversion element, and systematically cultivates one main electrode of the Darlington type transistor. By configuring a Sotafunaro circuit, it is not necessary to reset the signal output line connected to the main electrode, and multiple photoelectrons can be connected from one signal output line without intervening a reset operation. This allows sequential signals to be output from the conversion element.

[Example] Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a circuit configuration diagram of a first embodiment of a photoelectric conversion device of the present invention.

Components that are common to those shown in FIG. 4 are designated by the same reference numerals, and explanations thereof will be omitted.

In FIG. 1, 1l is a Darlington bibolar transistor whose base region is connected to a storage capacitor 3. In FIG. Reference numeral 12 denotes a load resistor, which forms an emitter follower together with the Darlington bibolar transistor 11 when the MOS transistor 7 is turned on.

The operation of the sensor pixel is the same as the conventional example explained in Figs. 4 and 5, but after the signal is accumulated in the storage capacitor 3, it is turned on by the output from the horizontal shift register HSR. Through MOS transistor 7,
A signal is output to the horizontal output line 6 by the emitter follower operation. During emitter follower operation, the base is in a floating state, but the Darlington bibolar transistor 1
Since the current amplification factor of 1 is extremely high, a drop in the base potential can be ignored. This kind of signal readout does not require resetting the horizontal output line 6 as in the conventional method, and uses a shift register that outputs both scanning pulses PHI and PH2 in synchronization, and converts the signal of one row of pixels into one horizontal line. It can be output from the output line.

In addition, the output is lower than the signal stored in the storage capacitor 3 due to the resistance division between the ON resistance of the MOS transistor 7 and the load resistor 12, but the output is lower than the signal stored in the storage capacitor 3.
It is easy to make the N resistance sufficiently small, and it is possible to output a much higher level signal to the horizontal output line 6 than in the conventional method using capacitance division.

FIG. 2 is a circuit diagram of a horizontal signal transfer section of a second embodiment of the photoelectric conversion device of the present invention.

In the figure, 13 is a MOS transistor that acts as a load resistance of the emitter follower when it is in the ON state. MOS transistor l3 is connected to each Darlington type bibolar transistor l1. The operation of such a horizontal transfer section is the same as in the case of FIG. appears in

In addition, in the first embodiment shown in FIG. The contribution to this is small.

FIG. 3 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied.

In the figure, an image sensor 201 in which optical sensors are arranged in an area is subjected to television scanning by a vertical scanning section 202 and a horizontal scanning section 203.

The signal output from the horizontal scanning section 203 is sent to the processing circuit 20.
4 and output as a standard television signal.

Drive vanoles φMm, φs++ φH! of vertical and horizontal scanning units 202 and 203. I φ vs. φv+
．． φv2 etc. are supplied by the driver 205. The driver 205 is also limited by the controller 206.

[Effects of the Invention] As explained above, according to the photoelectric conversion device of the present invention,
By electrically connecting the control electrode of a Darlington type transistor to the signal output side of the photoelectric conversion element, and electrically connecting a load means to one main electrode of the Darlington type transistor, an emitter follower circuit is constructed. , it is not necessary to reset the signal output line connected to the main electrode, and signals can be sequentially output from a plurality of photoelectric conversion elements from one signal output line without intervening a reset operation. Furthermore, the signal accumulated in the base with the signal capacity A I'll <, fr, as in the conventional case, can be output as is to the signal output line.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the photoelectric conversion device of the present invention. FIG. 2 is a circuit diagram of a horizontal signal transfer section of a second embodiment of the photoelectric conversion device of the present invention. FIG. 3 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied. FIG. 4 is a circuit diagram of a conventional photoelectric conversion device. FIG. 5 is a timing chart for explaining the operation of the charging conversion device. l: sensor pixel, 2: output line, 3: storage capacitor, 4: M
OS} transistor, 5: MOS}-transistor, 6: horizontal output line, 7: MOS transistor, 8: MOS transistor, 9: horizontal drive line, lo: MOS transistor,
11: Darlington type bibolar transistor, 12:
Load resistance, 13:1i103 transistor, HSR:
Horizontal shift register, VSR: Vertical shift register, A
MP: Preamplifier.

Claims (2)

[Claims] (1) A control electrode of a Darlington transistor is electrically connected to the signal output side of a photoelectric conversion element capable of accumulating photoelectrically converted charges, and a load means is electrically connected to one main electrode of the Darlington transistor. A photoelectric conversion device constitutes an emitter follower circuit and reads out a signal from the main electrode. (2) The photoelectric conversion element is a photoelectric conversion element that accumulates photoelectrically converted charges in a control electrode region of a semiconductor transistor and extracts an amplified signal from one main electrode region of the semiconductor transistor. photoelectric conversion device.