JPH0316331A - Data link protection system - Google Patents

Abstract

PURPOSE:To protect a data link without standby line by connecting one of spare bits for data link signal transmission to a transmission side and a reception side monitoring control sections selectively by means of a switching circuit. CONSTITUTION:When the fault of a line A is detected in a 1st equipment or a 2nd equipment, switching circuits SW1, SW2 (transmission side and reception side) are operated based on the control of monitoring control sections MPU1, MPU2 of a 1st or 2nd equipment side. Then the monitoring control sections MPU1, MPU2 are connected to spare bits for sending a data link signal multiplexed or demultiplexed in each of multiplex/demultiplex circuits MUXB, MUXb connected to other line such as a line B. Thus, the data link is protected without a standby line.

Description

[Detailed Description of the Invention] [Summary] Regarding a data link protection method for communication between supervisory control units of a transmission device, it is possible to protect the data link without a backup line, and if there is a line that can communicate. The purpose is to provide a data link protection method that always allows data link communication, by using a line that has a multiplexing/demultiplexing circuit and a line interface circuit that has a line error rate detection function.
In a protection method for a data link that communicates between supervisory control units, a switch circuit that selectively connects the supervisory control unit to one of the multiplex/separate circuits of the plurality of lines is provided, and the line used for the data link is protected. When the line interface circuit detects a fault in the line, the supervisory control section switches the switch circuit to perform data link communication using another line.

[Industrial Application Field] The present invention relates to a data link protection system for communicating between monitoring and control units of transmission devices.

In recent years, with the expansion of transmission networks, there has been a demand for control and monitoring from a location away from the transmission device itself, such as centralized monitoring and remote monitoring. The data link communication method is a method that performs low-speed data communication using the service bit of the main signal in order to control and monitor opposing devices, and is widely used. However, if a failure occurs in the main signal due to disconnection of the main signal or deterioration of the error rate, data link communication becomes impossible, so protection is required.

[Conventional technology]

FIG. 4 shows a conventional data link protection system.

In the figure, A' to D' are normal lines, and P is a protection line. L
IIJA~D, P and LIU a~d, p
are line interface circuits that have functions such as communication with the opposing device, detection of main signal abnormalities such as reception error rate and signal interruption, and power supply to intermediate repeaters; is a multiplex/separate circuit, SWI
' and SW2' are switch circuits that switch an abnormal line to a protection line. MPUI and MPu2 are supervisory control units,
It has a control function for its own device, a function to monitor the LIU and switch SW based on the result, and a function to perform data link communication with the opposing device. Note that this figure shows only one direction, and the reverse direction is omitted, but the same structure is used.

Each multiplexing/separating circuit MUX has 6
4/K}Iz are connected and 1
．． If multiplexed at 544 Mb/s and PCM 30, the same 30
channels are connected, making it 2.048Mb/s
The signals are multiplexed and transmitted, and the receiving side separates them into the original channels.

The data link signal from the supervisory control unit MPljl is connected to the multiplex circuit MUXA and transmitted to the opposite device through line A', and on the opposite equipment side, the separation device MUXa' extracts the data link signal and sends it to the supervisory control unit MPU2. There are spare bits for the above 2.048Mb/s, etc.
Data link signals are sent using the spare bits.

When a failure occurs in line A', the switch circuit SW is switched under the control of the MPU, and MLIXA', MU
Xa' is connected to LIUP and LIUp2, thereby protecting the data link.

That is, if line A' becomes faulty in Fig. 4, this will be detected at line interface L{Ua' and MtlX
This is notified to MPU2 through a', and MPU2
'lPU1 to backup line P (MPU2→MP not shown)
MPt
ll operates Ski to switch the line from A' to P.

In this case, the main signal is also sent through the protection line P.

By switching the switch SW, the main signal of the line A' is also switched to the protection line P. The protection line P is switched to even when lines B' and C'D' are out of order, but line A', which carries data link signals, has a high priority, and lines B l , C
Even if I or D' is faulty, if line A' is faulty, then A'
is switched to line P preferentially.

[Problems to be solved by the invention] In this conventional system, a protection line is always required, line A' is given priority when switching to the protection line, and if a failure occurs in both lines A' and P, However, there are problems such as data link communication becoming impossible.

An object of the present invention is to provide a data link protection method that allows data link protection without a backup line, and allows data link communication whenever there is a communicable line.

[Means to solve the problem]

In the data link protection system of the present invention, a plurality of lines A, B, C, and D are connected between first and second devices facing each other via multiplexing/demultiplexing circuits MUXA=D and MUXa-d, respectively. Spare bits for transmitting a data link signal are provided in each of the multiplexing/demultiplexing circuits MUXA-D, MUXa=d, and among the spare bits for transmitting a data link signal that are multiplexed or separated in each of the multiplexing/demultiplexing circuits MUXA-D, MUXa=d. One is
Switch circuit SW. ．． At SW2, it is selectively connected to the monitoring control units MPU1 and MPII2 on the transmitting side and the receiving side. No protection line P is provided.

[For production]

In this device, a switch circuit (on the transmitting side or receiving side) SW. , S.W. The multiplexing/demultiplexing circuit MUXA, M that connects to line A by operating
When the spare bits for data link signal transmission, which are multiplexed or separated in each UXa, are connected to the supervisory control units MPII1 and MPυ2, the data link communication between the supervisory control units MPUI and MPU2 is transferred to line A (
(spare bin for data link signal transmission).

When a fault in line A is detected on the first device side or the second device side, under the control of the monitoring control units MPU1 and MPU2 on the first device side or the second device side, Switch circuit (sending side or receiving side) SW1,
By operating the SWZ, the supervisory control units MPU1 and MPU2 are multiplexed in each of the multiplexing/demultiplexing circuits MUXB and MtlXb that connect to another line, for example, line B.
Alternatively, connect it to the separated spare bit for data link signal transmission. In this way, the supervisory control unit MPtl
Data link communication between MPU 2 and MPU 2 is switched so that it is performed through line A (spare bit for data link signal transmission).

〔Example〕

2 and 3 show switch circuits SW, SW. A specific example is shown below.

FIG. 2 is a diagram showing the structure of the first embodiment of the present invention.

As shown in FIG. 2, the transmitting side switch circuit SW.
are multiplexing/demultiplexing circuits MUX8~D connected to each line,
Switches SWa-SWd and buffers 7 BIII'A to BUF are connected to the spare bits for data link signal transmission multiplexed in each of MUXa to d.
The output side of each switch SWa=SWd is pulled up to H (high) level via a pull-up resistor. Further, the switch circuit SWz on the receiving side includes a buffer BUFa=BIJFd inserted into each line and a buffer BUFe connected to their common output terminal.

The switches SWa=SWd are turned on/off under control from the supervisory control unit U1. Buffer BUFa=BUFd is an open collector output. The data link signal from the supervisory control unit MPU is in a general normal formant.

Now, when the key υ1 closes the switch SWa and SWb-SWd are open, the spare bit of the line BD becomes H (high), and the line A becomes H and L according to the data link signal.

Since the output terminals of the buffers BUFa to BtlFd are wired OR of the oven collector output, the signal of line 8 is obtained at the output terminal, and this is sent to the MPU 2 through the buffer BLIFe.

If a fault occurs in line A, the line interface circuit LIUa on the receiving side (not shown in Fig. 2, but the above-mentioned As in the configuration of FIG. 4, the line interface circuits LIUA-D and LIUa-d
(provided with
Notify J2. Upon receiving this, I'lPtl2 connects another line, for example, from MPLl2 (not shown) to MPU of line B.
MP through a one-way line (a line in a configuration in which the transmitting and receiving sides of the configurations in Figures 1 and 2 are reversed)
Notify the UI of the failure of line A. Upon receiving this, the supervisory control unit MPUI switches to the switch circuit (transmission side in Figure 2) S-1.
, and connect MPtll to another line, for example, B. At this time, switching of the data link signal transmission bit is performed by opening SWa and closing SWb. As a result, the data link signal transmission bits of lines A, C, and D become high, and the data link signal transmission bits of line B become H and L in accordance with the data link signal. Banfa BUF
Since the output terminal of a-BUFd is a wired ○R of open collector output, the signal of data link signal transmission bit 1 of line B is obtained at the output terminal, and this is the signal of the data link signal transmission bit 1 of line B.
It is sent to MPU2 through Fe. In this way, MPU1
, MP02 data link communication is now performed through line B.

If line B also fails, line switching is performed in the same way, and the line is switched to another line, for example C.

The same applies below. This switch circuit is the one on the sending side
W. In this case, there is a switch S W a = S': i d, which is turned on and off to switch the line, but on the receiving side Memo Sh there is no switch, it is wired OR and switching is done automatically. (The transmitted signal appears).

In Figure 4, if line A fails, it is switched to protection line P.
If the protection line P is also at fault, the data link communication will be interrupted. According to the present invention, data link communication can be continued as long as there is a healthy line.

No backup line is required. However, if a line fails, the transmission of the main signal passing through the line will be interrupted.

However, in the configuration shown in FIG. 2 described above, since the receiving side of the data link transmission signal line is wired ○R of the oven collector output, the data link transmission signal line is connected to the monitoring control unit MPUI on the transmitting side. Errors, such as noise, occurring on a line other than the line connecting the data link may appear in the wired OR output of the open collector output on the receiving side of the data link transmission signal line.

A second embodiment of the invention, described below, solves this problem.

FIG. 3 is a diagram showing a horizontal command according to a second embodiment of the present invention.

As shown in FIG. ,SW
, in the transmission side switch circuit SW, the multiplex/
multiplexed in each of the separation circuits MIIXA-D,
All spare bits for data link signal transmission on each line are connected to the output of the monitoring control unit (MP01) on the sending side, and the switch circuit SW2 on the receiving side is connected to the multiplexing/separating circuit MUXa connected to each line. = switches SWa' to SWd' connected to the spare bits for data link signal transmission separated in each of d and buffer B
A buffer BUFe is connected to their common output terminal, and is connected to a monitoring control unit MPU2.

Switches SWa' to SWd' are supervisory control unit IIP
It is turned on/off under control from U2.

Now MPU2 closes switch SWa' and SWb' ~
When SWd' is open, only the spare bit for data link signal transmission on line 8 is connected to the supervisory control unit U2 via the buffer BUFe. Therefore, the signal of line A is obtained at the output end and is sent to MPU2 through buffer BUFe. According to this precept, other line B
, C, and D are not connected to the supervisory control unit MPU2, so errors occurring on lines other than the line connecting the data link transmission signal line to the supervisory control unit MPU2, such as noise, may be transmitted to the receiving side. It never appears.

In the configuration shown in FIG. 3, when a fault occurs in line A, the line interface circuit LIUa on the receiving side detects the line failure based on the error rate, for example, and transmits it to MUXa, as in the case shown in FIG. The monitor control unit MPIJ2 is notified by the output. Upon receiving this, the MPU2 switches the switch circuit SW. MPt to another line, for example B.
Connect l2. At this time, switching of the data link signal transmission bit is performed by opening SWa' and closing SWb'. This allows the buffer BtlFe
A data link signal transmission bit signal of the line B is obtained at the input end of the line B, and is sent to the MPU 2 through BLIFe. In this way, data link communication between MPU1 and MPu2 is performed through line B. If line B also fails, line switching is performed in the same way, and the line is switched to another line, for example C.

The same applies below. This switch/disconnect circuit is the one on the receiving side. In this case, there are switches SWa' to SWd', which are turned on and off to switch lines, but the SW on the transmitting side has no switches, and the monitoring control unit MPU1 uses spare bits for data link transmission of all lines. It is connected.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide a data link communication system that can protect a data link with a simple switch circuit without a backup line, and that allows communication whenever there is a communicable line.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a circuit diagram showing a first embodiment of the invention, Fig. 3 is a circuit diagram showing a second embodiment of the invention, and Fig. 4 is a circuit diagram showing a second embodiment of the invention. is a block diagram showing a conventional method. [Explanation of symbols] MUX^~D. MUXa to d... multiplex/separate circuits,
A, B, C, D... line, sw. , swz...switch circuit, MPU1, MPU2... monitoring control unit, SWa-d
+ SWa' ~ d'...ON/○FF switch, BUFa~BUFe...buffer, A'~D'...normal line, P...protection line, LIUA~D, P, LIUa~ d, p = line interface circuit, MUXA' to D'MUXa' to d' - multiplex/separate circuit, SWI', SW2'...switch circuit. Patent originator Fujitsu Limited Patent application agent

Claims (1)

[Claims] 1. Multiplexing/demultiplexing circuits (MUXA to D, MUXa to d) between the first device and the second device facing each other
Spare bits for data link signal transmission are provided in each of the plurality of lines (A, B, C, D) connected via or one of the separated spare bits for data link signal transmission is
The switch circuits (SW_1, SW_2) provided on the first device side and the second device side selectively control the sending side and receiving side monitoring control units (MPU1, MPU2).
) is a data link protection method. 2. The switch circuits (SW_1, SW_2) are connected to the multiplex/demultiplex circuits (MUXA to D, MU
ON/OFF for selectively connecting one of the spare bits for data link signal transmission multiplexed in each of
OFF switches (SWa-d), and on the receiving side, the multiplexing/demultiplexing circuits (MUXA-D, MUXa-d)
All of the spare bits for data link signal transmission separated in each of
2. The data link protection system according to claim 1, wherein the data link protection system is connected to the MPU 2) as a wired-OR connection with an open collector output. 3. The switch circuits (SW_1, SW_2) are connected to the multiplex/demultiplex circuits (MUXA to D, MU
The spare bits for data link signal transmission, which are multiplexed in each of Xa to Xd), are all connected to the output of the monitoring control unit (MPU1) on the transmitting side, and the multiplexing/demultiplexing on the receiving side Circuit (MUXA~D, MUXa
ON/OFF switches (SWa' to d' ) The data link protection system according to claim 1. 4. Multiplex/separate circuit (MUX) and line interface circuit (LIU) with line error rate detection function
In a data link protection method for communicating between supervisory control units (MPUs) using lines with A switch circuit (SW) is provided to selectively connect a supervisory control unit to one of the circuits, and when a line interface circuit of a line used for data link detects a fault in the line, the supervisory control unit switches the switch circuit. , a data link protection method characterized by using another line for data link communication.