JPH0316738U - - Google Patents
Info
- Publication number
- JPH0316738U JPH0316738U JP7699589U JP7699589U JPH0316738U JP H0316738 U JPH0316738 U JP H0316738U JP 7699589 U JP7699589 U JP 7699589U JP 7699589 U JP7699589 U JP 7699589U JP H0316738 U JPH0316738 U JP H0316738U
- Authority
- JP
- Japan
- Prior art keywords
- output
- phase comparator
- clock signal
- digital data
- setting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はこの考案の一実施例の構成を示すブロ
ツク図。第２図はこの考案の一実施例の変形例の
構成を示すブロツク図。第３図は従来例の構成を
示すブロツク図。第４図は位相比較器の動作のタ
イミング図。第５図は入力デジタルデータの伝送
レート高速のときの比較出力に対する浮遊容量の
影響を示す模式図。
２……位相比較器、３……ループフイルタ、４
……電圧制御発振器、５……読み取りクロツク信
号生成回路、６……制御信号発生回路、７……電
圧発生器。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2 is a block diagram showing the configuration of a modification of one embodiment of this invention. FIG. 3 is a block diagram showing the configuration of a conventional example. FIG. 4 is a timing diagram of the operation of the phase comparator. FIG. 5 is a schematic diagram showing the influence of stray capacitance on comparison output when the input digital data transmission rate is high. 2... Phase comparator, 3... Loop filter, 4
. . . voltage controlled oscillator, 5 . . . read clock signal generation circuit, 6 . . . control signal generation circuit, 7 . . . voltage generator.
Claims (1)
タルデータを読み取るクロツク信号とを位相比較
して、前記デジタルデータの変化点から前記クロ
ツク信号の予め定められた変化点まで高または低
電位レベルの出力を発生し、その後すぐ、または
一定期間後に前記クロツク信号の1/2周期間逆の
レベル出力を発生し、かつ他の期間においては出
力端がハイ・インピーダンスとなる位相比較器と
、該位相比較器の出力端に接続され、かつ前記位
相比較器の出力端がハイ・インピーダンスのとき
の出力電位を設定する設定手段と、前記位相比較
器の出力と前記設定手段による設定出力とが重畳
された信号を入力とするループフイルタと、前記
ループフイルタの出力が制御電圧として供給され
る電圧制御発振器と、前記電圧制御発振器の発振
出力周波数を前記デジタルデータの伝送レートに
応じた分周比で分周して前記クロツク信号を生成
する読み取りクロツク信号生成回路とを備えたＰ
ＬＬ回路において、前記デジタルデータの伝送レ
ートに応じて前記位相比較器の出力端がハイ・イ
ンピーダンスのときの設定手段による設定出力を
変化させると共に、前記ループフイルタにオフセ
ツト電圧を印加する電圧発生手段とを備えたこと
を特徴とするＰＬＬ回路。 Compares the phase of serially input digital data and a clock signal for reading the digital data, and generates a high or low potential level output from a change point of the digital data to a predetermined change point of the clock signal. , a phase comparator that generates an output with an opposite level for a half period of the clock signal immediately or after a certain period of time, and whose output terminal becomes high impedance during other periods; and an output of the phase comparator. a setting means connected to the output end of the phase comparator and setting an output potential when the output end of the phase comparator is in high impedance; and inputting a signal in which the output of the phase comparator and the setting output of the setting means are superimposed. a voltage controlled oscillator to which the output of the loop filter is supplied as a control voltage; and a read clock signal generation circuit for generating a clock signal.
In the LL circuit, voltage generating means changes the setting output of the setting means when the output end of the phase comparator is in high impedance according to the transmission rate of the digital data, and applies an offset voltage to the loop filter. A PLL circuit characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7699589U JPH0749870Y2 (en) | 1989-07-01 | 1989-07-01 | PLL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7699589U JPH0749870Y2 (en) | 1989-07-01 | 1989-07-01 | PLL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0316738U true JPH0316738U (en) | 1991-02-19 |
| JPH0749870Y2 JPH0749870Y2 (en) | 1995-11-13 |
Family
ID=31618964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7699589U Expired - Lifetime JPH0749870Y2 (en) | 1989-07-01 | 1989-07-01 | PLL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0749870Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999027826A1 (en) * | 1997-12-01 | 1999-06-10 | Nippon Crescent Co., Ltd. | Method of providing foods on rotary food table and apparatus therefor |
| JP4988940B1 (en) * | 2011-03-07 | 2012-08-01 | 三耶子 神田 | Frying pan lid |
-
1989
- 1989-07-01 JP JP7699589U patent/JPH0749870Y2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999027826A1 (en) * | 1997-12-01 | 1999-06-10 | Nippon Crescent Co., Ltd. | Method of providing foods on rotary food table and apparatus therefor |
| JP4988940B1 (en) * | 2011-03-07 | 2012-08-01 | 三耶子 神田 | Frying pan lid |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0749870Y2 (en) | 1995-11-13 |
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