JPH0318043A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH0318043A JPH0318043A JP1151911A JP15191189A JPH0318043A JP H0318043 A JPH0318043 A JP H0318043A JP 1151911 A JP1151911 A JP 1151911A JP 15191189 A JP15191189 A JP 15191189A JP H0318043 A JPH0318043 A JP H0318043A
- Authority
- JP
- Japan
- Prior art keywords
- elements
- mask layout
- template
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電算機を用いて設計を行う半導体集積回路の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit, which is designed using a computer.
従来の技術
近年、半導体集積回路は、大規模化の一途をたどり電算
機による自動設計の要求が高まっている。以下に従来の
マスクレイアウト自動設計について説明する。第３図は
、回路図である。第３図において、５，６，１２，１３
，１４．１５は抵抗．７，８，９，１０，１１は、トラ
ンジスタ、１６は正電源，１７は負電源を示している。2. Description of the Related Art In recent years, the scale of semiconductor integrated circuits has continued to increase, and there has been an increasing demand for automatic design using computers. Conventional automatic mask layout design will be explained below. FIG. 3 is a circuit diagram. In Figure 3, 5, 6, 12, 13
, 14.15 is the resistance. 7, 8, 9, 10, and 11 are transistors, 16 is a positive power source, and 17 is a negative power source.
第４図は，第３図の回路図に対応する従来の方法で作成
したマスクレイアウト図である。第４図において、１８
，１９．２５，２６．２７．２８は抵抗、２０．２１，
２２．２３．２４はトランジスタである。従来の方法で
は、第３図に示すような回路図中の各素子の相対的位置
関係を電算機によって抽出し、それをマスクレイアウト
上に再現し、第４図のようになっていた。FIG. 4 is a mask layout diagram created by a conventional method corresponding to the circuit diagram of FIG. 3. In Figure 4, 18
, 19.25, 26.27.28 is resistance, 20.21,
22, 23, and 24 are transistors. In the conventional method, a computer extracts the relative positional relationship of each element in a circuit diagram as shown in FIG. 3, and reproduces it on a mask layout as shown in FIG. 4.
発明が解決しようとする課題
上記従来のマスクレイアウトでは、各素子間のすき間（
デッドスペース）が多くなる傾向があった。特に、バイ
ボーラ半導体集積回路では、素子間同士に素子間の分離
拡散層を必要とし、これがデッドスペースを一層大きな
ものとし，ひいては、チップサイズを大きくしてしまう
という問題点を有していた。Problems to be Solved by the Invention In the conventional mask layout described above, the gaps (
dead space) tended to increase. In particular, bibolar semiconductor integrated circuits require isolation diffusion layers between elements, which has the problem of increasing dead space and, in turn, increasing chip size.
本発明は、上記従来の課題を解決するもので、電算機に
よるマスクレイアウト自動設計において、マスクレイア
ウト上の素子の最適配置構成を提供することを目的とす
る。The present invention is intended to solve the above-mentioned conventional problems, and an object of the present invention is to provide an optimal arrangement configuration of elements on a mask layout in automatic mask layout design using a computer.
課題を解決するための手段
この目的を達成するために本発明は、いくつかの基本的
な配置パターン〈テンプレート〉を用意し、その中から
回路上の素子同士の位置関係に最も近いテンプレートを
選び、素子の配置を行う構成を有している。Means for Solving the Problem In order to achieve this object, the present invention prepares several basic layout patterns (templates), and selects the template that is closest to the positional relationship between the elements on the circuit. , has a configuration for arranging elements.
作用
この構戒によって、抵抗、トランジスタ、容量を同類素
子でまとめて合理的に配置できる。また、分離拡散層に
よるデッドスペースが減少し、チップ面積を最少にする
ことができる。Effect: This structure allows resistors, transistors, and capacitors to be arranged rationally by grouping similar elements together. Furthermore, the dead space due to the separation diffusion layer is reduced, and the chip area can be minimized.
実施例
第１図は，本発明の一実施例におけるテンプレートであ
る。１は正電源側抵抗のプレート、２はトランジスタの
プレート、３は負電源側抵抗のプレートである。第２図
は、本発明の一実施例を示す、マスクレイアウト図で第
４図で対応するものには、同一の番号が付してある。Embodiment FIG. 1 is a template in one embodiment of the present invention. 1 is a plate of the resistor on the positive power supply side, 2 is a plate of the transistor, and 3 is a plate of the resistor on the negative power supply side. FIG. 2 is a mask layout diagram showing one embodiment of the present invention, and parts corresponding to those in FIG. 4 are given the same numbers.
第３図は、第２図のマスクレイアウト図に対応する回路
図である。FIG. 3 is a circuit diagram corresponding to the mask layout diagram of FIG. 2.
まず、第３図の素子の位置関係より第１図のテンプレー
トが選択され、第３図より抽出した素子を第１図のテン
プレートに合わせて配置していく。正電源側の抵抗５．
６を正電源側抵抗のプレートｌへ配置する。トランジス
タ７．８，９，１０．１１をトランジスタのプレート２
へ配置する。負電源側の抵抗１２．１３，１４．１５を
負電源側抵抗のプレート３へ配置していく。その後、対
応するマスクレイアウト上の素子に置き換えられ，第２
図に示す、マスクレイアウト図が形成される。第２図の
マスクレイアウト図は、回路図とのイメージにも似かま
っており、同類素子をまとめて配置しているため、分離
拡散層によるデッドスペースも減少し、電算機によるマ
スクレイアウトの自動設計を容易にし、またチップ面積
を最少にする。First, the template shown in FIG. 1 is selected based on the positional relationship of the elements shown in FIG. 3, and the elements extracted from FIG. 3 are arranged in accordance with the template shown in FIG. 1. Resistance on the positive power supply side 5.
6 is placed on the plate l of the positive power supply side resistor. Transistors 7.8, 9, 10.11 on transistor plate 2
to be placed. Resistors 12.13 and 14.15 on the negative power supply side are arranged on the plate 3 of the negative power supply side resistance. After that, it is replaced with the element on the corresponding mask layout, and the second
The mask layout diagram shown in the figure is formed. The mask layout diagram in Figure 2 is similar to a circuit diagram, and because similar elements are arranged together, the dead space caused by the separation diffusion layer is reduced, and the mask layout can be automatically designed using a computer. and minimize the chip area.
発明の効果
以上のように本発明によれば、いくつかの基本配置パタ
ーン（テンプレート〉を用意し、その中から回路図上の
素子同士の位置関係に最も近いテンプレートを選び、素
子を配置することによって、従来の方法におけるマスク
レイアウトより合理的に配置ができ、回路図とのイメー
ジにも近く、また面積を大きく減少させることのできる
優れたマスクレイアウトの自動設計を実現することが可
能である。Effects of the Invention As described above, according to the present invention, several basic layout patterns (templates) are prepared, the template that is closest to the positional relationship between the elements on the circuit diagram is selected, and the elements are arranged. As a result, it is possible to realize automatic design of an excellent mask layout that can be arranged more rationally than in the conventional method, closely resembles a circuit diagram, and can greatly reduce the area.
第１図は、本発明の一実施例で用いた基本的配置パター
ン（テンプレート）図、第２図は、本発明の一実施例で
形成したマスクレイアウト図、第３図は本発明の一実施
例適用回路に対応する回路図、第４図は、従来の方法に
よるマスクレイアウト図である。
１・・・・・・正電源側抵抗のプレート、２・・・・・
・トランジスタのプレート、３・・・・・・負電源側抵
抗のプレート、４・・・・・・テンプレート、５，６．
１２．１３，１４．１５．１８．１９，２５，２６．２
７，２８，・・・・・・抵抗．７．８．９，１０．２０
，２１，２２，２３．２４・・・・・・トランジスタ、
１６・・・・・・正電源、１７・・・・・・負電源。FIG. 1 is a basic arrangement pattern (template) diagram used in an embodiment of the present invention, FIG. 2 is a mask layout diagram formed in an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. The circuit diagram corresponding to the example application circuit, FIG. 4, is a mask layout diagram according to a conventional method. 1... Positive power supply side resistor plate, 2...
- Transistor plate, 3...Negative power supply side resistor plate, 4...Template, 5, 6.
12.13, 14.15.18.19, 25, 26.2
7,28,...Resistance. 7.8.9, 10.20
, 21, 22, 23.24...transistor,
16...Positive power supply, 17...Negative power supply.
Claims (1)
を、複数個の配置位置基本パターン（テンプレート）を
もつトランジスタ群、抵抗群、容量群から、回路図上の
素子同士の位置関係と最も近い前記基本パターンを選び
、それに従って各素子を配置することを特徴とする半導
体集積回路の製造方法。The mask layout for each functional block of a semiconductor integrated circuit is determined by selecting the basic pattern that is closest to the positional relationship between the elements on the circuit diagram from transistor groups, resistor groups, and capacitor groups that have multiple layout position basic patterns (templates). 1. A method for manufacturing a semiconductor integrated circuit, which comprises selecting a semiconductor integrated circuit and arranging each element accordingly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1151911A JP2672655B2 (en) | 1989-06-14 | 1989-06-14 | Method for manufacturing semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1151911A JP2672655B2 (en) | 1989-06-14 | 1989-06-14 | Method for manufacturing semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0318043A true JPH0318043A (en) | 1991-01-25 |
| JP2672655B2 JP2672655B2 (en) | 1997-11-05 |
Family
ID=15528891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1151911A Expired - Lifetime JP2672655B2 (en) | 1989-06-14 | 1989-06-14 | Method for manufacturing semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2672655B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7930219B2 (en) | 2001-09-17 | 2011-04-19 | Formfactor, Inc. | Method and system for designing a probe card |
| JP2022189173A (en) * | 2021-06-10 | 2022-12-22 | 株式会社日立製作所 | Rendering system |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2746762B2 (en) | 1990-02-01 | 1998-05-06 | 松下電子工業株式会社 | Layout method of semiconductor integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591856A (en) * | 1978-12-29 | 1980-07-11 | Ibm | Semiconductor integrated circuit chip structure |
| JPS59211246A (en) * | 1983-05-17 | 1984-11-30 | Nec Corp | Analog ic master slice system |
| JPH01132134A (en) * | 1987-11-18 | 1989-05-24 | Toshiba Corp | Arrangement and wiring method of electronic circuit |
-
1989
- 1989-06-14 JP JP1151911A patent/JP2672655B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591856A (en) * | 1978-12-29 | 1980-07-11 | Ibm | Semiconductor integrated circuit chip structure |
| JPS59211246A (en) * | 1983-05-17 | 1984-11-30 | Nec Corp | Analog ic master slice system |
| JPH01132134A (en) * | 1987-11-18 | 1989-05-24 | Toshiba Corp | Arrangement and wiring method of electronic circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7930219B2 (en) | 2001-09-17 | 2011-04-19 | Formfactor, Inc. | Method and system for designing a probe card |
| JP2022189173A (en) * | 2021-06-10 | 2022-12-22 | 株式会社日立製作所 | Rendering system |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2672655B2 (en) | 1997-11-05 |
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