JPH03181294A - Data transmission system - Google Patents

Abstract

PURPOSE:To prevent the normal processing of a master station from being stopped due to lots of occurrence of interrupt requests by storing fault information once to a 1st error latch means and outputting an interrupt request signal to a central processing circuit of the master station when the circulation of polling call is finished. CONSTITUTION:Fault information when a fault state takes place in a system is once stored in a 1st error latch circuit 11. Then when circulation of a polling call to all slave stations is finished, the fault information latched in the 1st error latch circuit 11 is latched by a 2nd error latch circuit 12 to output an interrupt request signal INT to a central processing circuit if the master station. Thus, the stop of the normal processing of the central processing circuit is surely avoided.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Field of Industrial Application) The present invention collects data by sequentially making polling calls from one master station to a plurality of (N) slave stations. In a 1-to-N data transmission system, even if an abnormal state occurs in the system simultaneously or consecutively, this method reliably prevents the normal processing operation of the central processing circuit of the master station from stopping due to frequent interrupt requests. The present invention relates to a data transmission system.

(Prior Art) For example, in the field of electric power systems, remote monitoring and control devices have been widely used for the purpose of monitoring and controlling objects to be monitored. As a data transmission system for this remote monitoring and control device, a one-to-N type data transmission system has been adopted. That is, in this one-to-N data transmission system, one master station sequentially makes polling calls to a plurality (N) of slave stations to collect data.

By the way, such data transmission systems are usually equipped with various self-diagnosis functions, such as a CRC code check and a parity code check, to determine whether the received frame is correct or not, and which check the operating status of the own station equipment. ing. If any abnormal condition is detected as a result of the check, an error signal is output, and a request is made to the central processing circuit of the own station to handle the abnormality by means of an interrupt.

FIG. 2 is a block diagram showing an example of the hardware configuration of a data transmission-related portion of a data transmission device provided in a master station and a slave station in this type of one-to-N type data transmission system. In FIG. 2, the data transmission device includes a direct memory access (hereinafter referred to as DMA) circuit 21.
, a transmission/reception control circuit 22 , a transmission circuit 23 , a frame check code generation circuit 24 , a frame check code determination circuit 25 , a reception circuit 26 , and an interrupt processing circuit 27 .

Such a data transmission device operates under the control of a transmission/reception control circuit 22. That is, in the case of a transmission operation,
The DMA circuit 21 reads data from a memory circuit (not shown) connected to the end of the address bus 29 and data bus 28, and DMA transfers the data to the transmitting circuit 23. Next, in the transmitting circuit 23, the DMA transferred data is subjected to parallel-to-serial conversion, and after a frame check code generated by the frame check code generation circuit 24 is added, processing such as encoding and level conversion is performed. After that, the data is sent to the transmission path 210.

On the other hand, in the case of a reception operation, the received data is subjected to processing such as level conversion and decoding by the reception circuit 26, and then serial-to-parallel conversion. is determined. As a result, when it is determined that the received frame is correct, the DMA circuit 21 performs DMA transfer of data from the receiving circuit 26 to a memory circuit (not shown). If it is determined that the received frame is incorrect, the received frame is discarded and an error status signal 2C is output from the frame check code determination circuit 25 to the interrupt processing circuit 27.

In addition to this, during the series of operations described above, each circuit constantly performs self-diagnosis to see if its own circuit is operating correctly, and as a result, the occurrence of an abnormal condition is detected. Then, an error status signal is output to the interrupt processing circuit 27. For example, in FIG. 2, when an abnormal condition occurs in the transmitting circuit 23, an error status signal 2a is output, and when an abnormal condition occurs in the frame check code generating circuit 24, an error status signal 2b is output.

When the error status signals 2a to 2c are inputted to the interrupt processing circuit 27, the error status and accompanying status signals are sent to the transmission/reception control circuit 2.
2, and after holding it, an interrupt request signal INT is output to a central processing circuit (not shown).

FIG. 3 is a block diagram showing an example of the configuration of a conventional interrupt processing circuit 27. As shown in FIG. In FIG. 3, the interrupt processing circuit 27 includes an error holding circuit 31, an error station address holding circuit 32, and a 3-state buffer 33.

In the interrupt processing circuit 27, the error holding circuit 31 holds the error status signals 3a1 to 3aM when they are input, and as a result, an interrupt request signal INT is immediately output to a central processing circuit (not shown). In addition, in the error station address holding circuit 32, when the error status signals 381 to 3aM are input, the address value of the station that was transmitting and receiving at the time of the error occurrence is
It is input from the transmission/reception control circuit 22 and held.

This held address value can be read by a central processing circuit (not shown) via the 3-state buffer 33 and the data bus.

However, the data transmission system as described above has the following problems.

In other words, the master station in a 1-to-N data transmission system is a station that sequentially makes polling calls to each slave station and collects data, so it is constantly transmitting and receiving data. . Therefore, if an abnormal state occurs in multiple slave stations at the same time, or if an abnormal state occurs in the transmission path connecting the master station and the slave stations, a response to a polling call may not be returned correctly, and the frame check/tsuku code determination circuit 25 may In a case where received frame abnormalities are detected continuously, a state is reached in which interrupt request signals INT are outputted to the central processing circuit one after another. As a result, there is a problem in that the central processing circuit becomes busy with routine processing, and normal processing operations stop.

In addition, in order to understand in which slave station an abnormal condition has occurred, the station address value is held when an abnormal condition occurs in a slave station. In this case, for example, if the address is 16 bits, A register for holding 16 bits is also required, resulting in a problem that the register length increases.

(Problems to be Solved by the Invention) As described above, in the conventional 1-to-N data transmission system, when abnormal conditions occur simultaneously or consecutively, the normal processing operation of the central processing circuit of the master station is interrupted. There have been problems in that the register length has to be increased in order to detect abnormal conditions.

An object of the present invention is to reliably prevent the normal processing operation of the central processing circuit of a master station from stopping due to frequent interrupt requests even when abnormal states occur in the system simultaneously or consecutively; It is an object of the present invention to provide an extremely reliable data transmission system capable of grasping which slave station an abnormal state has occurred while suppressing an increase in register length.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention collects data by sequentially making polling calls from one master station to a plurality of (N) slave stations. In a 1-to-N data transmission system, when an abnormal state occurs in the system, the first error holding means that holds the abnormality information at that time and the polling call to all slave stations are terminated. A second error holding means latches and holds the abnormality information of the first error holding means in synchronization with a cycle completion signal indicating the first error holding means, and a second error holding means latches and holds the abnormality information of the first error holding means. The master station is equipped with a counter value holding means for holding a counter value indicating the polling order of the slave stations in which the error has occurred, and when the error information is latched in the second error holding means, the error information is sent to the central processing circuit of the master station. The error information in the second error holding means and the counter value in the counter value holding means are read out by the central processing circuit as necessary.

(Function) Therefore, in the data transmission system of the present invention, even if an abnormal state occurs in the system simultaneously or consecutively, the abnormality information at that time is temporarily stored in the first error holding means, and all children When one cycle of polling calls to the station is completed, the abnormality information stored in the first error holding means is latched by the second error holding means, and an interrupt request signal to the central processing circuit of the master station is output. This makes it possible to avoid the central processing circuit being busy with abnormal processing due to frequent interrupt requests, and stopping normal processing operations.

Furthermore, when an abnormal condition occurs, a counter value indicating the polling order of the slave stations is stored in the counter value holding means, and when a round of polling calls for all slave stations is completed, the counter value stored in the counter value holding means is stored in the counter value holding means. Since the value is read by the central processing circuit, there is no need to store the address value of the slave station where the abnormal condition has occurred, and it is possible to grasp which slave station the abnormal condition has occurred in while suppressing the increase in register length. can.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of an interrupt processing circuit in a data transmission device provided on the master station side of an l-to-N data transmission system according to the present invention. The configuration of the data transmission device provided on the slave station side is the same as that shown in FIG. 2, and the configuration of the data transmission device provided on the master station side is the same as the interrupt processing circuit 27 in the one shown in FIG. Only one has the configuration shown in FIG. Also,
In this embodiment, there are M types of error detection items and N number of slave stations.

In FIG. 1, the interrupt processing circuit of this embodiment has a first
The error holding circuit 11, the second error holding circuit 12, the OR circuit 13, the 3-state buffer 14, the decoder 15, the OR circuit 16, and N J- flip-flop circuits serving as counter value holding means. 171-17N and 3
- state buffer 18.

Here, the first error holding circuit 11 receives a plurality (M) of error status signals 1a1 to 1aM as input, and when an abnormal state occurs in the system, it holds abnormality information at that time. Further, the second error holding circuit 12 is
It latches and holds the abnormality information of the first error holding circuit 11, and synchronizes with the input of the -cycle end signal 1b.
An interrupt request signal INT is output to a central processing circuit (not shown) via an OR circuit 13, and abnormality information of the second error holding circuit 12 is sent to a 3-state buffer 14,
It is read out by the central processing circuit via the data bus.

On the other hand, the decoder 15 receives as input the station counter value from the counter in the transmission/reception control circuit 22, decodes it, and divides it into N signals IC1 to lcN for each slave station. Further, the OR circuit 16 inputs the error status signals lal to 1aM, calculates the logical sum of these signals, and outputs the result. Furthermore, the flip-flops 171 to 17N on J- input the output signals IC1 to 1cN from the decoder 15 to the J terminal, respectively, and hold the output signal from the OR circuit 16 as the CK terminal input. The station counter value, which is information, is read out by a central processing circuit (not shown) via the 3-state buffer 18 and the data bus.

In this case, the error status signals 1a1 to 1aM are information signals indicating the received frame judgment result in the frame check code judgment circuit 25 and the self-diagnosis result of each circuit, respectively. Furthermore, the round completion signal 1b is a signal indicating that polling calls to all slave stations have been completed.

Further, the station counter value is a counter value indicating which slave station is currently being polled.

Next, the operation of the one-to-N data transmission system configured as described above will be explained.

In FIG. 1, if error 3 occurs during the polling call of the first station, error status 1a
3 is set, and this abnormal state is held in the first error holding circuit 11, and at the same time, the signal 1c1, which is the current station counter value "1" decoded by the decoder 15, is held in the flip-flop 171 at J-. Ru. Next, if error 1 occurs during the polling call for the third attribute, the error status lal is set, and this abnormal state is held in the first error holding circuit 11, and at the same time the current station counter value is The signal 1c3 decoded by the decoder 15 is
− is held by a flip-flop 173. In this way, error information and error station numbers until the polling call for all N slave stations is completed are as follows:
It is held in the first error holding circuit 11 and J- flip-flops 171 to 17N.

When the polling calls to all N slave stations are completed, a round completion signal 1b indicating this is set.
In synchronization with this, the abnormal state of the first error holding circuit 11 is held in the second error holding circuit 12. At the same time, an interrupt request signal INT is outputted via the OR circuit 13 to a central processing circuit (not shown). Also, the abnormality information of the second error holding circuit 12 is read out by the central processing circuit via the 3-state buffer 14 and the data bus, and is also sent to the flip-flops 171 to 1 in J-.
The station counter value, which is the 7N held information, is read out by the central processing circuit via the 3-state buffer 18 and the data bus.

As described above, in the 1-to-N data transmission system of this embodiment, the abnormality information (error information) at the time when an abnormal state occurs in the system is stored in the first error holding circuit 11.
When the polling calls to all slave stations have completed one round, the error information held in the first error holding circuit 11 is latched in the second error holding circuit 12, and the central processing of the master station is performed. Interrupt request signal IN for the circuit
Since T is output, it is possible to reliably prevent the central processing circuit from being busy with abnormal processing due to the frequent occurrence of interrupt request signals and stopping the normal processing operation of the central processing circuit, which is the case in the past. becomes possible. In addition, in the past, the station address value was stored, but when an abnormal condition occurs, the counter value indicating the polling type of the slave station is stored in flip-flops 171 to 17N in J- (the flag corresponding to each slave station is stored). is set and held), and then read out by the central processing circuit when the polling calls to all slave stations have completed one cycle, so there is no need to store the address value of the slave station where an abnormal condition has occurred. It becomes possible to grasp in which slave station an abnormal state has occurred while suppressing an increase in register length. In other words, in a 1-to-N data transmission system, the master station controls the order in which polling calls are made, so as long as the order of the slave stations in which an abnormal condition occurs is known, it is possible to make detailed calls as before. This is because there is no need to hold up to the station address value.

[Effects of the Invention] As explained above, according to the present invention, even if an abnormal state occurs in the system simultaneously or consecutively, the normal processing operation of the central processing circuit of the master station can be prevented from being stopped due to frequent interrupt requests. It is possible to provide an extremely reliable data transmission system that can reliably prevent the occurrence of abnormal conditions, and can determine which slave station has experienced an abnormal state while suppressing an increase in register length.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of an interrupt processing circuit in a data transmission device provided on the master station side of a 1-to-N data transmission system according to the present invention, and FIG. 2 is a 1-to-N data transmission system. FIG. 3 is a block diagram showing an example of the structure of the conventional interrupt processing circuit shown in FIG. 2. FIG. . DESCRIPTION OF SYMBOLS 11... First error holding circuit, 12... Second error holding circuit, 13... OR circuit, 14... 3-state buffer, 15... Decoder, 16... OR
Circuit, 171-17N...Flip-flop on J-,
18...3-state buffer.

Claims (2)

[Claims] (1) In a 1-to-N data transmission system in which a single master station makes polling calls to multiple (N) slave stations in order to collect data, if an abnormal state occurs in the system, the a first error holding means that holds abnormality information at the time; and latching the abnormality information of the first error holding means in synchronization with a round completion signal indicating that polling calls to all the slave stations have been completed. and second error holding means for holding the error information on the master station side, and transmitting an interrupt request signal to the central processing circuit of the master station at the time when the abnormality information is latched in the second error holding means. A data transmission system characterized by outputting data. (2) In a 1-to-N data transmission system in which a single master station makes polling calls to multiple (N) slave stations in order to collect data, if an abnormal state occurs in the system, the a first error holding means that holds abnormality information at the time; and latching the abnormality information of the first error holding means in synchronization with a round completion signal indicating that polling calls to all the slave stations have been completed. and a counter value holding means for holding a counter value indicating the polling order of the slave station in which the abnormal state has occurred at that time when the abnormal state occurs, on the master station side. In preparation for this, when the abnormality information is latched in the second error holding means, an interrupt request signal is output to the central processing circuit of the master station, and the abnormality information of the second error holding means and the counter A data transmission system characterized in that the counter value of the value holding means is read out by the central processing circuit.