JPH0318145A - Network synchronizing system - Google Patents

Abstract

PURPOSE:To stably synchronize an entire network system by always selecting a normal clock signal for synchronization. CONSTITUTION:The clock signal of main transmission line system is frequency- divided until its frequency goes to the frequency in common to that of the clock signal of a LAN system with use of a frequency division means 10, and the clock signal of the LAN system is frequency-divided until its frequency goes to the frequency in common to that of the clock signal of the main transmission line system. A monitor control means 30 monitors the clock signals of both systems, and controls a selection means 40. And a clock generating means 50 is synchronized with the frequency-divided clock signal of the system being operated normally selected by the selection means 40. Thereby, it is possible to always synchronize the entire network system by synchronizing with one normal clock signal.

Description

[Detailed Description of the Invention] [Summary] Regarding a network synchronization method for a digital network including a backbone digital transmission line and a local area network, a common clock common to both systems is determined from the clock signals of the backbone digital transmission line and the local area network. The purpose is to provide a network synchronization method that stably synchronizes the entire network by generating a clock signal and synchronizing it with the common clock of normally operating systems. l-th dividing signal
a second frequency dividing means that divides the frequency of the clock signal of the local area network system, and a monitoring control means that monitors the clock signals of the two systems and generates a signal for selecting the signal of the normal system. and a selection means for selecting either the output of the first frequency division means or the output of the second frequency division means in response to a selection signal from the supervisory control means; , clock generation means for generating a clock signal, the monitoring control means monitors the clock signals of the two systems, and the selection means selects the frequency-divided clock signal of the system in which the clock signal is operating normally. The clock generator is selected to operate in synchronization with the clock signal.

[Industrial application field]

The present invention relates to a network synchronization system for a digital network including a backbone digital transmission line and a local area network.

When constructing a network of digital transmission lines, it is necessary to synchronize the entire network.

The synchronization method is to install a high-precision oscillator in the master station, transmit a reference clock from it, and make the network synchronization devices of each station dependent, thereby synchronizing the entire network.

This reference clock is generated by extracting the repetition frequency of the main signal. The main signal of the backbone transmission line is audio equivalent to 24
(1.5 MHz) and a multiplexing rate of 96 audio channels (6 MHz). Also,
The local area network uses a clock signal of N times 8 kHz (varies depending on the multiplexing capacity).

Such digital networks require a network synchronization system that has a plurality of clock systems and can stably synchronize the entire network even if a failure occurs in one clock system.

[Prior Art] FIG. 4 is a diagram illustrating a conventional digital network.

In the conventional example shown in FIG. 4, a master station 100 with a high-precision oscillator
It consists of slave stations 210 and 220 each having a phase-locked oscillator that oscillates in synchronization with the high-precision oscillator of the master station 100, and a local area network (hereinafter referred to as LAN) 30i consisting of a parent node 31i and slave nodes 32i to 3ni. has been admonished.

Here, i is represented as l and 2 assuming that there are two LANs.

In this example, the slave stations 210 and 220 of the backbone digital transmission line (hereinafter referred to as the backbone transmission line), the LAN 301,
302 is connected to the parent nodes 3l1 and 312 using a TTC standard 2 Mbps interface.

[Problem to be solved by the invention]

Recently, LANs have been widely adopted, and connections with backbone transmission lines and interconnections between LANs have become necessary.

However, since each LAN uses its own transmission speed, it is difficult to connect between different companies, and when a connection is necessary, the parent node of the LAN uses the TTC standard 2Mbps interface. The only way is to connect.

Also, for the same reason, up until now it has not been possible to connect LANs between different companies.

Furthermore, with conventional network synchronization systems, it is not possible to extract clock signals from various types of transmission lines, and when a failure occurs in the clock signal system, the system becomes an independent synchronization system, causing clock signal slips and reducing line quality. I was letting it happen.

The present invention generates a common clock common to both systems from the clock signals of the backbone transmission line and the LAN, and generates the clock signal in synchronization with the common clock of the system that is operating normally, thereby ensuring a stable network. The purpose is to provide a network synchronization method that synchronizes the entire network.

[Means to solve the problem]

FIG. 1 shows a bronc diagram illustrating the principle of the invention.

In the block diagram of the principle of the present invention shown in FIG. 1, 10 is a first frequency dividing means that divides the frequency of the clock signal of the backbone transmission line system, and 20 is a second frequency dividing means that divides the frequency of the clock signal of the LAN system. 30 is a supervisory control means that monitors the clock signal of the core transmission line system and the clock signal of the LAN system and generates a signal for selecting a normal system signal; 40 is a supervisory control means Means 30
The output of the first frequency dividing means 10 and
50 is a selection means for selecting one of the outputs of the second frequency dividing means 20;
This is a clock generation means that generates a clock signal, and providing such means is a means for solving this problem.

[For production]

The clock signal of the main transmission line system is frequency-divided by the first frequency dividing means 10 until it reaches a frequency common to that of the clock signal of the LAN system.

On the other hand, the frequency of the LAN system clock signal is divided by the second frequency dividing means 20 until it reaches a frequency common to that of the trunk transmission line system clock signal.

On the other hand, the monitoring control means 30 monitors the clock signal of the trunk transmission line system and the clock signal of the LAN system, and selects the selection means 4.
0, a selection signal is sent to select a system with a normal clock signal. When both systems are normal, the frequency-divided clock signal of the main transmission line system is set to be selected.

By synchronizing the clock generating means 50 with the frequency-divided clock signal of the normally operating system selected by the selecting means 40, the entire digital network is always synchronized with one normal clock signal. It becomes possible to synchronize. [Example] The gist of the present invention will be specifically explained below with reference to Examples shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating an example of a digital network according to the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG.
This is an example in which two systems of each LAN system clock are manually operated, and as the first frequency dividing means 10 explained in FIG.
Two frequency divider circuits A and 1 that divide the core transmission line system clock
1, 12, the second frequency dividing means 20, two frequency dividing circuits B, 2l, 22, which divide the frequency of the LAN system clock, and the supervisory control 1,000-stage 30, which monitors the clock signals of four systems, and according to the monitoring results. , a supervisory control circuit 3 selection stage 40 which generates a selection signal for selecting a normally operating system, and a backbone transmission line system clock, LA, which is manually operated for two systems each.
Switches (hereinafter referred to as SW) 41 and 42 select one of the N system clocks, and one of the trunk transmission line system clock and LAN system clock selected from the two systems. SW43, as a clock generation stage 50, multiplies the outputs of a phase synchronized oscillator 5I that oscillates in synchronization with the frequency-divided clock signal of the output of SW43 and a phase synchronized oscillator 5l, and generates the clock signal necessary for the digital network. This is an example in which a frequency multiplier circuit 52 is used to generate the signal.

In the above example, in order to ensure stable operation of the digital network, two systems of the main transmission line system clock and two systems of the LAN system clock are input, and the supervisory control circuit 31 and SW
4 L SW4 Select the system that is operating normally. When both systems are normal, set the system to be connected with priority in advance. Here, there are two systems of human power, but there is no problem even if there is one system.

8kHz is used as the common clock for the main transmission line system clock and LAN system clock, and the outputs of the frequency multiplier circuit are 8kHz, 64kHz, 1.5MHz, and 6M.
Outputs Hz.

By taking precautions as described above, it becomes possible to synchronize the entire network in synchronization with the clock signal of the system that is always operating normally.

FIG. 3 shows an example of a digital network employing the above-described method, in which the phase synchronized oscillators of slave stations 210 and 220 oscillate in synchronization with the high-precision oscillator of master station 100.

The slave stations 210 and 220 are connected through parent nodes 311 and 312 of the LAN 30 L 302, and the entire network is synchronized with the high precision oscillator of the master station 100.

In this configuration, the LAN 301 and the LAN 30 2 are connected to each other via the SW, and for example, the slave station 220
When a clock signal disconnection occurs between LAN 302 and LAN 302, the SW of slave node 332 of LAN 302 is
By switching to the opposite side, from the LAN301 side,
It is possible to receive a clock signal and synchronize the LAN 302.

〔Effect of the invention〕

According to the present invention as described above, it is possible to provide a network synchronization method that can stably synchronize the entire network by always selecting and synchronizing a normal clock signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the principle of the present invention, FIG. 2 is a block diagram explaining an embodiment of the present invention, FIG. 3 is a diagram explaining an example of a digital network according to the present invention, and FIG. 4 is a conventional diagram. Figures illustrating an example digital network are shown, respectively. In the figure, 10 is the first frequency dividing means, 1112 is the frequency dividing circuit A1, 20 is the second frequency dividing means, 21 and 22 are the frequency dividing circuit B, 30 is the supervisory control means, 3l is the supervisory control circuit, and 40 is the frequency dividing means. Selection means, 41, 42, 43 are switches, 50 is a clock generation means, 51 is a phase synchronized oscillator, 52 is a frequency multiplication circuit, 100 is a master station, 210, 220 are slave stations, 301, 302 are LANs, 311 to 312 indicates a parent node, and 321 to 3n2 indicate subordinate nodes. A block diagram for explaining the principle of the present invention.A block diagram for explaining an embodiment of the present invention.A diagram for explaining an example of a digital network according to the present invention.FIG. 3

Claims (1)

[Claims] A synchronization method for a digital network including a backbone digital transmission line and a local area network, comprising: a first method for frequency-dividing a clock signal of the backbone digital transmission line system;
a second frequency dividing means (20) for dividing the frequency of the clock signal of the local area network system; Monitoring control means (30
), and the output of the first frequency dividing means (10) and the second frequency dividing means (
a selection means (40) for selecting one of the outputs of 20); and in synchronization with the output selected by the selection means (40),
clock generating means (50) for generating a clock signal; the monitoring and controlling means (30) monitors the clock signal of the backbone digital transmission line system and the clock signal of the local area network system; A network synchronization method characterized in that a frequency-divided clock signal of a system in which the clock signal is operating normally is selected by (40), and the clock generation means (50) is operated in synchronization with the clock signal. .