JPH03181878A - Photoelectric switch - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse modulation type photoelectric switch in which a light receiving element detects pulsed light emitted from a light projecting element.

Regarding chi.

[Prior Art] Conventionally, pulse modulation type photoelectric switches (hereinafter referred to as photoelectric switches) emit, for example, pulse-modulated light from a light emitting element, which is received by a light receiving element, and receives this light reception signal. In some cases, a switching output is obtained by integrating the signal using an integrating circuit in order to further remove electrical noise, and then inputting the signal to a binarizing circuit and comparing the integrated output value with a predetermined level.

The above-mentioned integration circuits are generally constructed from circuits that utilize charging and discharging of capacitors, and the time constant is determined by a resistor and a capacitor.

[Problem B to be solved by the invention] However, as mentioned above, conventional photoelectric switches use an integrating circuit that utilizes the charging and discharging of capacitors, so the operating time may be shortened due to variations in elements such as resistors and capacitors. There are variations, and the time it takes to reach a certain standard level also differs depending on changes in the magnitude of the received light signal.
There was a drawback in that it affected the reliability of switching.

[Means for Solving the Problems] The present invention has been made based on the above-mentioned problems, and its purpose is not only to improve reliability by using an integrating circuit configured without using elements such as capacitors, but also to improve reliability. The purpose of the present invention is to provide a photoelectric switch that is suitable for downsizing.

That is, the photoelectric switch of the present invention includes: a signal generation circuit that outputs a transmission pulse signal of a predetermined frequency; a light emitting element driven by the transmission pulse signal; and a light receiving element that receives light emitted from the light emitting element. , a latch circuit that latches the light reception pulse signal from the light receiving element with a synchronization pulse synchronized with the transmission pulse signal and detects the presence or absence of the light reception pulse, a first counter that counts the presence of the light reception pulse, and a light reception circuit. a counter circuit comprising a second counter that indicates the absence of a pulse;
When there is a light reception pulse in the detection signal of the latch circuit, the second counter is reset and a synchronization pulse is sent to the first counter, and when there is no light reception pulse, the first counter is reset and the second counter is reset. It consists of a counter control circuit that sends a signal based on the synchronization pulse to the counter.

[Function] In the present invention, depending on the result of the presence or absence of a light reception pulse latched by the latch circuit, when there is a light reception pulse, the light reception is performed while sending a synchronizing pulse to the first counter that counts the existence of a light reception pulse. The second counter that counts when there is no pulse is reset, and when there is no received pulse, the first counter is reset and the second counter is reset.
The device sends a synchronizing pulse to the counter of the device, which allows the signal generated by the device to be detected digitally in a stable manner.

[Example] Hereinafter, an example of the photoelectric switch of the present invention will be described based on the drawings.

FIG. 1 is a block diagram illustrating the general configuration of a photoelectric switch of the present invention.

The signal generator 101 generates a transmission pulse signal q2 of a predetermined frequency.
a is generated and output to the light emitting element drive circuit 102, and a synchronization pulse 2b synchronized with the transmission pulse signal 2a is output to the latch circuit 107.

The light projecting element driving circuit 102 receives the transmission pulse signal 2a and converts the level of the signal into a signal that can drive the light projecting element 103. The light projecting element 103 is driven by the output signal of the light projecting element driving circuit 1'02 and is output as an optical signal. This optical signal is received by the light receiving element 104 and converted into an electric signal, amplified to a desired level by the amplifier 105, and "l 11
The latch circuit 1 is converted into a binary signal 2d of “O°”.
07 is input. This latch circuit 107 latches this binary signal 2d in synchronization with the synchronization pulse signal 2a, and if light from the light emitting element is received, a detection signal 1a is generated.
If no light is received, a detection signal lb is output to the counter control circuit 108. In the counter control circuit 10g, if the detection signal 1a of the latch circuit is output (light receiving state), the second counter 109b heliset signal R2 is output.
is output and reset, and the delayed signal 2c of the synchronizing pulse 2b is output to the first counter 109a. If the detection signal 1b is output (in a state where no light is being received), the first counter 109a outputs the heli-set signal R1. The delay signal 2C is then output to the second counter. The counter circuit 109 determines that light has entered when the first counter counts a predetermined number of times, and outputs an output 1g indicating that light has entered, and similarly, when the second counter counts a predetermined number of times, it determines that light has entered. It is determined that the light is not blocked (hereinafter referred to as light shielding), and outputs an output 1g indicating that the light is shielded. The output circuit 110 converts the level of the signal into a desired external output signal and outputs the signal.

FIG. 2 shows a latch circuit 107, a counter control circuit 108, and a counter circuit 109 in the photoelectric switch of the present invention.
An example of a specific circuit diagram is shown below.

Further, FIG. 3 is a timing chart of each signal in the circuit shown in FIG. 2.

In FIG. 2, the latch circuit 107 is a D flip-flop 107, hereinafter referred to as D-F/F.

). This D-F/F 107 inputs the binary signal 2d from the D terminal, and also outputs the positive logic output terminal Q and A detection signal 1a and a detection signal 1b are output from the negative logic output terminal Q. (See Fig. 3.) As can be seen from Fig. 3, the detection signal 1a and the detection signal 1b are the noise signal A1 included in the binary signal 2d. The noise generated in the circuit is removed from the signal. Here, the detection signal 1a is I
It indicates that the light was received at the time of IHII, and the detection signal 1b is IHII.
I shall indicate that no light is being received at the time of HII. Detection signal 1a output from this D-F/F 107
and 1b are transmitted to the counter control circuit 108.

The counter control circuit 108 includes AND gates 102a, 1
02b and a delay circuit 108C. First, the delay circuit 108C inputs the synchronizing pulse signal 2b and outputs a delayed signal 2c obtained by delaying the synchronizing pulse signal 2b. Note that the delay circuit 108c is not configured in the counter control circuit 108, but can be provided in, for example, a signal generation circuit to generate the delayed signal 2c, and the design can be changed as appropriate. Further, the delayed signal 2c may be a signal obtained by inverting the synchronizing pulse 2b.

Furthermore, the detection signal a and the delay signal 2c are input to the AND gate 102a, and the output 1c thereof is transmitted to the clock terminal of the first counter 109b. Similarly, the AND gate 1o2b receives the detection signal it) and the delay signal 2c, and its output 1d is transmitted to the clock terminal of the second counter 109a.

Furthermore, the counter control circuit 108 receives the input detection signal 1a.
, 1b are separately branched to transmit the detection signal 1a to the reset terminal of the second counter 109a, and to transmit the detection signal ib to the reset terminal of the first counter 109a.

1b are directly used as reset signals R1 and R2.

The counter circuit 109 has a first counter 109a and a second counter 109a.
counter 109b and R/S flip-flop 109c
It consists of Here, for example, the first and second counters are assumed to be ternary counters. The first counter 109a inputs the output 1c and counts the number of pulses, that is, the number of times the light is received, and when it reaches three times, the ripple carry terminal (hereinafter referred to as
It is called the RC terminal. ) from ripple hand Lee output le(
Hereinafter, this will be referred to as RC output. ), but if a reset signal is input from the reset terminal midway through, the count up to that point will be cleared. Note that the second counter 109
Similarly, in b, input the output 1d, count the number of pulses, that is, the number of times that no light is received, and when it reaches 3 times, output the RC output 1f from the RC terminal, but in the same way, a reset signal is sent from the reset terminal on the way. When input, clear the count up to that point. The R/S flip-flop 109c is the first. 2 counter l O9a.

In response to the RC output of 109b, the output signal 1 shown in FIG.
Output g to the external circuit.

Next, the operation of the circuit shown in FIG. 2 will be explained.

Now, assuming that there is a light reception signal at the rising edge of the synchronization pulse 2b (assuming that the binary signal 2d becomes H), the detection signal 1a is nH++ and the detection signal 1b is L 1
It becomes 1.

Therefore, AND gate 108a is opened and AND gate 1
Since o8b is closed, the output of AND gate 1°8a is
The delayed signal pulse 2C is output to the first counter 109a.
The output of the AND gate 108b is L''' and is input to the clock terminal of the second counter 109b.

At this time, the recent terminal of the first counter 109a has
Since "II L" is being input, this counter is in an enabled state and is counted up by the rising edge of the delay signal pulse 2C. When the count reaches 3, the RC output 1e is output.

However, when the light reception signal disappears before the count reaches 3 (the binary signal 2d is "L"), the detection signal 1a of the DF/F 107 becomes IILI+, the AND gate 108a closes, and the DF/F 107 The detection signal 1b is +
+H", the first counter 109a is reset. Therefore, the RC output 1e of the first counter 109a will not be output unless there is a light reception signal of three or more consecutive pulses in synchronization with the synchronization pulse 2b. In exactly the same way,
The RC output if of the second counter 109b is not output unless it detects that there is no light reception signal for three or more consecutive pulses in synchronization with the synchronization pulse 2b.

These RC signals 1e% 1f are input to an R/S flip-flop 109c to obtain an output signal 1g which is inverted each time each signal is detected. Therefore, this output signal 1g is generated when three or more pulses or more are consecutively detected to indicate that there is a light reception signal detected in synchronization with the synchronization pulse 2b.
'H°°, and then maintain this state until 3 or more consecutive pulses are detected to indicate that there is no light reception signal detected in synchronization with the synchronization pulse 2b.
Only when pulses or more are detected continuously does it invert to ""L u. Therefore, even if a noise signal synchronized with the synchronization signal 2b is detected, it is rare that it is detected in several pulses (three pulses in this case) in succession, and it is difficult to stably detect the signal emitted by itself. I can do it.

[Effects] As explained above, if this circuit is used, noise can be removed without using a C-R, and since it is detected digitally, fluctuations in response time due to element variations can be suppressed. Since everything can be constructed from logic circuits, it has the excellent feature that it can be easily miniaturized by C, etc., and it is possible to provide a small and highly reliable photoelectric switch.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit of an embodiment of the photoelectric switch of the present invention, FIG. 2 is a specific circuit diagram of this embodiment, and FIG. 3 is a timing chart of each signal. DESCRIPTION OF SYMBOLS 101...Signal generation circuit 102...Light emitter drive circuit 103...Light emitter 104...Light receiving element 105...Amplifier circuit 106...Binarization circuit 107...Latch circuit 108...Counter control circuit 108a, 108b---AND gate 108C...
Delay circuit 109...Count circuit 109a...First counter circuit 109b...Second counter circuit 110...Output circuit

Claims (1)

[Claims] (1) A signal generation circuit that outputs a transmission pulse signal of a predetermined frequency, a light emitting element driven by the transmission pulse signal, a light receiving element that receives light emitted from this light emitting element, and from this light receiving element. a latch circuit that latches the received light pulse signal with a synchronization pulse synchronized with the transmitted pulse signal and detects the presence or absence of the received light pulse; a first counter that counts the presence of the received light pulse; and a first counter that counts the presence of the received light pulse, and the absence of the received light pulse. a second counter that counts the number of pulses; and when there is a light reception pulse in the detection signal of the latch circuit, the second counter is reset and a synchronization pulse is sent to the first counter; and a counter control circuit that resets the first counter when there is no pulse and sends a signal based on the synchronization pulse to the second counter.