JPH03186033A - Signal transmission system - Google Patents

Signal transmission system

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Publication number
JPH03186033A
JPH03186033A JP32494989A JP32494989A JPH03186033A JP H03186033 A JPH03186033 A JP H03186033A JP 32494989 A JP32494989 A JP 32494989A JP 32494989 A JP32494989 A JP 32494989A JP H03186033 A JPH03186033 A JP H03186033A
Authority
JP
Japan
Prior art keywords
signal
output
input
signals
sent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32494989A
Other languages
Japanese (ja)
Inventor
Shinichi Sato
伸一 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP32494989A priority Critical patent/JPH03186033A/en
Publication of JPH03186033A publication Critical patent/JPH03186033A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To eliminate the need for exclusive control by enabling two signal input/output devices which transmit digital signals mutually to detect the sent signals from the opposite devices even when sending the signals through a couple of signal transmission lines simultaneously, and then enabling the both to send and receive the signals simultaneously even through one signal transmission line. CONSTITUTION:The sent signals sent from transmission parts A and B to the same signal transmission line 13 are multiplexed by signal multiplexing parts of signal input/output parts 1a and 2a and then signal demultiplexing parts demultiplex their sent signals and opposite-side sent signals from the multiplexed signals. Only the sent signal of each side is removed from the demultiplexed sent signal and the sent signal of the opposite side is inputted to a signal input part and thus received. The opposite-side signal input/output part also performs the same operation to receive the signal sent through the same signal transmission line 13. Both the parts A and B can send and receive the signals simultaneously through the one signal transmission line 13 and the need for exclusive control is eliminated.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、コンピュータの入出力装置、或は通信制御
装置の入出力インターフェースに関し、特に複数の入出
力装置で同時に信号の入出力を行なう信号伝送装置に関
するものである。
Detailed Description of the Invention (Industrial Application Field) The present invention relates to an input/output device of a computer or an input/output interface of a communication control device, and particularly to a signal input/output device that inputs/outputs signals simultaneously with a plurality of input/output devices. This relates to a transmission device.

〔従来の技術〕[Conventional technology]

従来、この種の信号伝送方式としては、第3図に示すも
のがあった。第3図は従来の信号伝送を行なうための回
路図であり、図において、(1)(2)はA側及びB側
の入出力インターフェース回路、(3) 、 (4)は
信号送信用ドライバ、(5) 、 (6)は信号受信用
レシーバ、(7) 、 (8)は送信信号の入力信号線
、(9) 、 (10)は受信信号の出力信号線、(1
1) 、 (12)は送受信を切り換えるための選択信
号線、(13)はA側およびB側入出力インターフェー
ス回路(1) 、 (2)間を接続するための信号伝送
路である。
Conventionally, as this type of signal transmission system, there has been one shown in FIG. Figure 3 is a circuit diagram for conventional signal transmission. In the figure, (1) and (2) are input/output interface circuits on the A side and B side, and (3) and (4) are signal transmission drivers. , (5) and (6) are receivers for signal reception, (7) and (8) are input signal lines for transmission signals, (9) and (10) are output signal lines for reception signals, (1
1) and (12) are selection signal lines for switching between transmission and reception, and (13) is a signal transmission line for connecting between the A-side and B-side input/output interface circuits (1) and (2).

次に、動作について説明する。A側の入出力インターフ
ェース回路(1)からB側の人出力インターフェース回
路(2)へ信号を送信する場合、A側の入出力インター
フェース回路(1)の選択信号線(11)を論理1にし
てドライバ(3)を動作可の状態にすると共に、レシー
バ(5)を動作不可の状態にする。一方、信号受信側で
あるB側の入出力インターフェース回路(2)は、選択
信号線(12)を論理Oにし、ドライバ(4)を動作不
可の状態にすると共に、レシーバ(6)を動作可の状態
にする。
Next, the operation will be explained. When transmitting a signal from the input/output interface circuit (1) on the A side to the human output interface circuit (2) on the B side, set the selection signal line (11) of the input/output interface circuit (1) on the A side to logic 1. The driver (3) is enabled and the receiver (5) is disabled. On the other hand, the input/output interface circuit (2) on the B side, which is the signal receiving side, sets the selection signal line (12) to logic O, disables the driver (4), and enables the receiver (6). state.

次いで、A側の入出力インターフェース回路(1)の送
信信号の入力信号線(7)より信号を人力することによ
り、ドライバ(3)から信号が出力され、信号伝送路(
13)を経由してB側の人出力インターフェース回路(
2)へ信号が伝えられる。この結果、B側の人出力イン
ターフェース回路(2)では、伝えられた信号をレシー
バ(6)が受は取り受信信号の出力fg号線(10)に
出力する。A側の人出力インターフェース回路(1)が
送信している間は、信号伝送路(13)は占有されるた
め、白側の人出力インターフェース回路(2)は、送信
することができないので、ドライバ(4)を動作不可状
態に保つ必要がある。一方、B側の入出力インターフェ
ース回路(2)からA側の入出力インターフェース回路
(1)へ信号を送信する場合は、B側の人出力インター
フェース回路(2)の選択信号線(12)を論理1にし
、ドライバ(4)を動作可の状態にすると共に、レシー
バ(6)を動作不可の状態にする。一方、信号受信側で
あるA側の入出力インターフェース回路(1)は、選択
信号線(11)を論理Oにすると共に、ドライバ(3)
を動作不可の状態に、レシーバ(5)を動作可の状態に
する。次いで、B側の人出力インターフェース回路(2
)の送信信号の入力信号線(8)より信号を入力するこ
とにより、ドライバ(4)から信号が出力され、信号伝
送路(13)を経由してA側の人出力インターフェース
回路(1)へ信号が伝えられる。A側の入出力インター
フェース回路(1)では、伝えられた信号をレシーバ(
5)が受は取り、受信信号の出力信号線(9)に出力す
る。入出力インターフェース回路(2)が送信している
間は、同じく信号伝送路(]3)が占有されているため
A側の人出力インターフェース回路(1)は送信するこ
とができないので、ドライバ(3)を動作不可の状態に
保つ必要がある。
Next, by manually inputting a signal from the input signal line (7) of the transmission signal of the input/output interface circuit (1) on the A side, the signal is output from the driver (3), and the signal is transmitted through the signal transmission line (
13) on the B side via the human output interface circuit (
A signal is transmitted to 2). As a result, in the B-side human output interface circuit (2), the transmitted signal is received by the receiver (6) and outputted to the received signal output line fg (10). While the human output interface circuit (1) on the A side is transmitting, the signal transmission path (13) is occupied, so the human output interface circuit (2) on the white side cannot transmit. (4) must be kept inoperable. On the other hand, when transmitting a signal from the B-side input/output interface circuit (2) to the A-side input/output interface circuit (1), the selection signal line (12) of the B-side human output interface circuit (2) is 1 to enable the driver (4) and disable the receiver (6). On the other hand, the input/output interface circuit (1) on the A side, which is the signal receiving side, sets the selection signal line (11) to logic O, and the driver (3)
The receiver (5) is made inoperable and the receiver (5) is made operable. Next, the B-side human output interface circuit (2
) by inputting a signal from the transmission signal input signal line (8), the signal is output from the driver (4), and is sent to the human output interface circuit (1) on the A side via the signal transmission line (13). A signal is transmitted. The input/output interface circuit (1) on the A side transmits the transmitted signal to the receiver (
5) receives the signal and outputs it to the output signal line (9) of the received signal. While the input/output interface circuit (2) is transmitting, the human output interface circuit (1) on the A side cannot transmit because the signal transmission path (3) is also occupied. ) must be kept inoperable.

(発明が解決しようとする課題) 従来の信号伝送方式は以上のように行なわれているので
、各人出力インターフェース回路の双方で同時に送信を
行なうと、信号伝送路上で互いに相手の送信データを潰
してしまうため、一方の入出力インターフェース回路か
らしか信号伝送を行なえず、従って、信号伝送時に一方
の人出力インターフェース回路間で信号送信停止、或は
信号受信停止等の排他制御を行なうことが必要となり、
信号伝送手順が複雑化する。又、各入出力インターフェ
ース回路の双方で同時にデータ送受信ができないため、
データ送信と受信とを時分割で行なう必要があり、デー
タ送受信に時間を要するなどの問題点があった。
(Problem to be solved by the invention) Since the conventional signal transmission method is performed as described above, if both output interface circuits of each person transmit data at the same time, each other's transmitted data will be destroyed on the signal transmission path. Therefore, signals can only be transmitted from one input/output interface circuit, and therefore, when transmitting signals, it is necessary to perform exclusive control between one input/output interface circuit, such as stopping signal transmission or stopping signal reception. ,
Signal transmission procedures become complicated. Also, since data cannot be transmitted and received simultaneously on both input and output interface circuits,
It is necessary to perform data transmission and reception in a time-division manner, which poses problems such as the time it takes to transmit and receive data.

この発明は上記のような問題を解消するためになされた
もので、双方が1つの信号伝送路で同時に信号の送受信
を行ない、排他制御を必要としない信号伝送方式を得る
ことを目的とする。
The present invention has been made to solve the above-mentioned problems, and aims to provide a signal transmission system in which both parties simultaneously transmit and receive signals on one signal transmission path and do not require exclusive control.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る信号伝送方式は第1及び第2の信号入出
力機器における各信号出力部間に信号伝送路を配すると
ともに、各信号入出力機器には、自己の信号出力部より
出力された信号と相手側信号出力部より出力された信号
を合成する信号合成部と、該合成信号より各出力信号を
分離する信号分離部と、これら分離された出力信号中、
自己の出力信号を除去し、相手側出力信号を信号入力部
へ出力する信号除去部とを設けたものである。
In the signal transmission method according to the present invention, a signal transmission path is arranged between each signal output section of the first and second signal input/output devices, and each signal input/output device has a signal output from its own signal output section. a signal combining section that combines the signal and the signal output from the signal output section of the other party; a signal separating section that separates each output signal from the combined signal; and a signal separating section that separates each output signal from the combined signal;
The device is provided with a signal removing section that removes its own output signal and outputs the other party's output signal to the signal input section.

〔作用〕[Effect]

この発明によれば、同一信号伝送路上に送信された各送
信部よりの送信号を、各信号人出力部における信号合成
部にて合成した後、これら合成信号より自己の送信信号
と相手側の送信信号とを信号分離部にて分離し、分離さ
れたこれら送信信号より自己の送信信号のみを除去し、
相手側の送信信号を信号入力部へ入力し相手信号を受信
する、また、一方、相手側信号入出力部においても同様
の作用を行ない、同一信号伝送路を介して送信されてき
た信号を受信する。
According to this invention, after the transmission signals from each transmitting unit transmitted on the same signal transmission path are combined in the signal combining unit in each signal output unit, these combined signals are used to combine the own transmission signal and the other side's transmission signal. A signal separation section separates the transmitted signal from the transmitted signal, and removes only the own transmitted signal from these separated transmitted signals.
Inputs the transmission signal of the other party to the signal input section and receives the other party's signal.On the other hand, the signal input/output section of the other party performs the same function and receives the signal transmitted via the same signal transmission path. do.

(実施例) 以下、この発明の一実施例を図について説明する。尚、
第1図において、第3図と同一符号は同−又は相当部分
を示す。図中、(IA) 、 (2A)は本実施例にお
けるA側、及びB側の入出力インターフェース回路、(
21) 、 (22)は検出抵抗、(23)(24) 
、 (25) 、 (26)は検出抵抗(21) 、 
(22)の電位差を検出するためのコンパレータ、(2
7) 、 (28) 、 (29) 。
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. still,
In FIG. 1, the same reference numerals as in FIG. 3 indicate the same or corresponding parts. In the figure, (IA) and (2A) are input/output interface circuits on the A side and B side in this embodiment, (
21), (22) are detection resistors, (23) (24)
, (25), (26) are the detection resistors (21),
A comparator for detecting the potential difference of (22), (2
7), (28), (29).

(30)は論理素子でNORゲート、(31) 、 (
32)は論理素子でANDゲート、(33) 、 (3
4)は論理素子でORゲートである。第2図は第1図の
動作を説明するための真理表である。
(30) is a logic element, which is a NOR gate, (31), (
32) is a logic element and is an AND gate, (33), (3
4) is a logic element and is an OR gate. FIG. 2 is a truth table for explaining the operation of FIG. 1.

次に本実施例の動作について説明する。A側の入出力イ
ンターフェース回路(IA)の送信信号の人力信号線(
7)とB側の入出力インターフェース回路(2A)の送
信信号の人力信号線(8)のそれぞれに第2図に示すよ
うな信号が人力されたときのA側の入出力インターフェ
ース回路(IAJ側の受信信号の出力信号線(9)の出
力信号について説明する。
Next, the operation of this embodiment will be explained. The human input signal line for the transmission signal of the input/output interface circuit (IA) on the A side (
7) and the input/output interface circuit on the A side (IAJ side) when a signal as shown in Fig. The output signal of the output signal line (9) of the received signal will be explained.

第2図に示す信号状態ケース1の場合、双方の送信信号
の人出力信号線(7) 、 (8) に論理0が人力さ
れているため、双方のドライバ(3) 、 (4)の出
力は論理Oとなり、電位差が無いので検出抵抗(21)
には電流が疏れず、コンパレータ(23) 、 (25
)の差動入力端子間の電位差も0となり、コンパレータ
(23) 、 (25)の出力はどちらも論理Oを出力
する。
In the case of signal state case 1 shown in Figure 2, since logic 0 is input to the human output signal lines (7) and (8) of both transmission signals, the outputs of both drivers (3) and (4) becomes logic O, and there is no potential difference, so the detection resistor (21)
The current does not flow through the comparators (23) and (25
) also becomes 0, and the outputs of the comparators (23) and (25) both output logic O.

このためNORゲート(z7)の出力は論理1となり、
ANDゲート(31)のゲートを開き、ANDゲート(
31)の出力に送信信号の入信分線(7)の入力信号で
ある論理Oが出力される。一方、NORゲート(29)
のゲートは閉じ、NORゲート(29)の出力は論理O
となり、ORゲート(33)の出力である受信信号の出
力信号線(9)には、B側の人出力インターフェース回
路(2A)の送信信号の入力信号線(8)と同じ論理0
の信号が出力される。次に、第2図に示す信号状態ケー
ス2の様に、双方の送信信号の人力信号線(7) 、 
(8)に論理1が入力された場合も、信号状態ケース1
と同じ様にドライバ(3) 、 (4)の出力が同した
め、検出抵抗(21)には電流が流れずコンパレータ(
23) 、 (25)の出力はどちらも論理Oとなる。
Therefore, the output of the NOR gate (z7) becomes logic 1,
Open the AND gate (31) and open the AND gate (31).
31), a logic O which is the input signal of the input branch line (7) of the transmission signal is output. On the other hand, NOR gate (29)
gate is closed and the output of the NOR gate (29) is logic O
Therefore, the output signal line (9) of the received signal, which is the output of the OR gate (33), has the same logic 0 as the input signal line (8) of the transmitted signal of the human output interface circuit (2A) on the B side.
signal is output. Next, as in signal state case 2 shown in Fig. 2, the human signal line (7) for both transmission signals,
Even if logic 1 is input to (8), signal state case 1
Similarly, since the outputs of drivers (3) and (4) are the same, no current flows through the detection resistor (21) and the comparator (
The outputs of 23) and (25) are both logic O.

従って、NORケート(27)のゲートか開き論理1と
なってANDゲート(31)へ人力される。その結果、
ANDゲート(31)のゲートが開き、論理1がORゲ
ート(9)の出力である受信信号の出力信号線(9)に
は送信信号の入力信号線(7)の人力信号である論理1
が出力される。この出力もB側の入出力インターフェー
ス回路(2A)の送信信号の人力信号線(8)の人力信
号と論理が同じになる。
Therefore, the gate of the NOR gate (27) opens and becomes logic 1, which is input to the AND gate (31). the result,
The gate of the AND gate (31) opens, and the output signal line (9) of the received signal, where the logic 1 is the output of the OR gate (9), receives the logic 1, which is the human input signal of the input signal line (7) of the transmission signal.
is output. This output also has the same logic as the human input signal of the human input signal line (8) of the transmission signal of the input/output interface circuit (2A) on the B side.

次に第2図に示す信号状態ケース3の様に、送信信号の
人力信号線(7)には論理O1もう一方の送信信号の人
力信号線(8)には論理1がそれぞれ人力された場合、
トライバ(3)の出力が論理O、トライバ(4)の出力
が論理1となり、ドライバ(3)とドライバ(4)の間
に電位差が生じ、検出抵抗(21)に電流が流れ、コン
パレータ(23)の人力にプラスの電位差が、コンパレ
ータ(25)の入力にマイナスの電位差かそれぞれ生じ
る。この結果、コンパレータ(23)の出力は論理1と
なり、コンパレータ(25)の出力は論理Oとなり、N
ORゲート(27)の出力は論理Oとなり、ANDゲー
ト(31)のゲートは閉し、NORゲート(29)のゲ
ートが開き、コンパレータ(25)の出力がNORケー
ト(29)で反転されて論理1か、受信信号の出力信号
線(9)に出力される。この出力もB側の入出力インタ
ーフェース回路(2A)の送信イコ号の人力信号線(8
)の入力信号と論理が同じになる。
Next, as in signal state case 3 shown in Fig. 2, when logic 0 is applied to the human input signal line (7) of the transmission signal and logic 1 is input to the human input signal line (8) of the other transmission signal. ,
The output of the driver (3) becomes logic O, the output of the driver (4) becomes logic 1, a potential difference is generated between the driver (3) and the driver (4), current flows through the detection resistor (21), and the output of the driver (23) becomes logic 1. ), a positive potential difference is generated at the input of the comparator (25), and a negative potential difference is generated at the input of the comparator (25). As a result, the output of the comparator (23) becomes logic 1, the output of the comparator (25) becomes logic O, and N
The output of the OR gate (27) becomes logic O, the gate of the AND gate (31) closes, the gate of the NOR gate (29) opens, and the output of the comparator (25) is inverted by the NOR gate (29) to become logic O. 1 or is output to the output signal line (9) of the received signal. This output is also the human input signal line (8) of the input/output interface circuit (2A) on the B side.
) has the same logic as the input signal.

次に第2図に示す信号状態ケース4の様に、送信信号の
入力信号線(7)には論理1、もう一方の送信信号の入
力信号線(8)には論理Oがそれぞれ人力された場合、
トライバ(3)とトライバ(4)の間には信号状態ケー
ス3と逆の電位差が生じ、検出抵抗(21)にも信号状
態ケース3とは逆方向に電流が流れコンパレータ(23
)の入力にマイナスの電位差が、コンパレータ(25)
の入力にプラスの電位差がそれぞれ生じる。この結果、
コンパレータ(23)の出力は論理Oとなり、コンパレ
ータ(25)の出力は論理1となり、NORゲート(2
7)の出力は論理Oとなり、ANDゲート(31)のゲ
ートは閉じ、NORゲート(29)のゲートが開き、コ
ンパレータ(25)の出力がNORゲート(29)で反
転されて論理Oが、受信信号の出力信号線(9)に出力
される。この出力もB側の入出力インターフェース回路
(2A)の送信信号の入力信号線(8)の入力信号と論
理が同じになる。この動作はB側の人出力インターフェ
ース回路(2A)側でも同じである。この様に双方の送
信信号の論理が同じ場合は自分の送信信号を、異なる場
合は、電流の向きを検出して、電流の向きから相手の送
信信号を分離し、双方が一対の信号伝送路(13)に信
号を同時に送信していても、互いに相手の送信信号を検
出することができる。
Next, as in signal state case 4 shown in Figure 2, logic 1 was manually input to the input signal line (7) of the transmission signal, and logic O was input to the input signal line (8) of the other transmission signal. case,
A potential difference opposite to the signal state case 3 is generated between the driver (3) and the driver (4), and a current flows in the detection resistor (21) in the opposite direction to the signal state case 3, and the comparator (23
) has a negative potential difference at the input of the comparator (25).
A positive potential difference is generated at the input of each. As a result,
The output of the comparator (23) becomes a logic O, the output of the comparator (25) becomes a logic 1, and the NOR gate (2
The output of 7) becomes a logic O, the gate of the AND gate (31) is closed, the gate of the NOR gate (29) is opened, the output of the comparator (25) is inverted by the NOR gate (29), and the logic O becomes the reception The signal is output to the signal output signal line (9). This output also has the same logic as the input signal of the input signal line (8) of the transmission signal of the input/output interface circuit (2A) on the B side. This operation is the same on the B-side human output interface circuit (2A) side. In this way, if the logic of the transmitted signals on both sides is the same, it will detect its own transmitted signal, and if it is different, it will detect the direction of the current and separate the other party's transmitted signal from the direction of the current. (13) Even if signals are transmitted simultaneously, each party can detect the other party's transmitted signals.

なお、上記実施例では、使用した論理素子の組合せでな
くても、論理的に同じであれば、他の組み合わせでも良
く上記実施例と同様の効果を奏する。
Note that in the above embodiment, it is not necessary to use the combination of logic elements used, but other combinations may be used as long as they are logically the same, and the same effects as in the above embodiment can be achieved.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明した通り、デジタル信号を相互伝送
する2機の信号入出力装置の双方が一対の信号伝送路で
同時に送信しても相手の送信信号を検出できる様にした
ので、各信号入出力機器で信号伝送を高速に行なうこと
ができる効果があ7る。
As explained above, this invention enables two signal input/output devices that mutually transmit digital signals to detect the other party's transmitted signal even if both transmit simultaneously through a pair of signal transmission paths. This has the advantage of being able to perform high-speed signal transmission at the output device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による信号伝送方式を示す
回路図、第2図は第1図に示した回路の動作を表わした
真理にツ第3図は従来の信号伝送方式を示す回路図。 CIA) 、 (2A)はA側およびB個人出力インタ
ーフェース回路、(3) 、 (4)はドライバ、’ 
(7)、(8)は送信信号の入力信号線、(9) 、 
(10)は受信信号の出力信号線、(13)は信号伝送
路、(21) 、 (22)は検出抵抗、(23) 、
 (24) 、 (25) 、 (26) はコンパレ
ータ、(27) 、 (28) 、 (29) 、 (
30)はNORゲート、(31) 、 (32)はAN
D ゲート、(33) 、 (34)  はORゲート
。 尚、図中同一符号は同−又は相当部分を示す。
Fig. 1 is a circuit diagram showing a signal transmission system according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing the operation of the circuit shown in Fig. 1, and Fig. 3 is a circuit diagram showing a conventional signal transmission system. figure. CIA), (2A) is the A side and B personal output interface circuit, (3), (4) is the driver,'
(7), (8) are the input signal lines of the transmission signal, (9),
(10) is the output signal line of the received signal, (13) is the signal transmission line, (21), (22) is the detection resistor, (23),
(24), (25), (26) are comparators, (27), (28), (29), (
30) is a NOR gate, (31) and (32) are AN
D gates, (33) and (34) are OR gates. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 第1及び第2の信号入出力機器における各信号出力部間
に信号伝送路を配するとともに、各信号入出力機器には
、自己の信号出力部より出力された信号と相手側信号出
力部より出力された信号を合成する信号合成部と、該合
成信号より各出力信号を分離する信号分離部と、これら
分離された出力信号中、自己の出力信号を除去し、相手
側出力信号を信号入力部へ出力する信号除去部とを内蔵
したことを特徴とする信号伝送方式。
A signal transmission path is arranged between each signal output section of the first and second signal input/output devices, and each signal input/output device has a signal output from its own signal output section and a signal output from the other party's signal output section. A signal synthesis section that synthesizes the output signals, a signal separation section that separates each output signal from the combined signal, removes its own output signal from these separated output signals, and inputs the output signal of the other party. A signal transmission method characterized by having a built-in signal removal section that outputs the signal to the section.
JP32494989A 1989-12-15 1989-12-15 Signal transmission system Pending JPH03186033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32494989A JPH03186033A (en) 1989-12-15 1989-12-15 Signal transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32494989A JPH03186033A (en) 1989-12-15 1989-12-15 Signal transmission system

Publications (1)

Publication Number Publication Date
JPH03186033A true JPH03186033A (en) 1991-08-14

Family

ID=18171429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32494989A Pending JPH03186033A (en) 1989-12-15 1989-12-15 Signal transmission system

Country Status (1)

Country Link
JP (1) JPH03186033A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5499269A (en) * 1993-07-20 1996-03-12 Hitachi, Ltd. Transmission-reception circuit
US7440494B2 (en) 2001-08-28 2008-10-21 Hitachi, Ltd. Method and system of bidirectional data transmission and reception
JP2009239830A (en) * 2008-03-28 2009-10-15 Nec Infrontia Corp Signal input/output state detection circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5499269A (en) * 1993-07-20 1996-03-12 Hitachi, Ltd. Transmission-reception circuit
US7440494B2 (en) 2001-08-28 2008-10-21 Hitachi, Ltd. Method and system of bidirectional data transmission and reception
JP2009239830A (en) * 2008-03-28 2009-10-15 Nec Infrontia Corp Signal input/output state detection circuit

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