JPH0318746B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to a newly proposed method for manufacturing a semiconductor device in which an electron flow passing through a barrier layer by a tunnel effect performs an amplification effect.

(b) Background of technology Microelectronics has become the basis for the development of modern industry and is also promoting major advances in social life. Currently, the mainstay of microelectronics is silicon (Si) semiconductor devices ranging from transistors to ultra-large-scale integrated circuit devices, and miniaturization of transistor elements has been promoted to improve characteristics and increase the degree of integration.

Furthermore, semiconductor devices using compound semiconductors such as gallium arsenide (GaAs), which have a much higher carrier mobility than silicon, have been developed in order to improve operating speed beyond the limits based on silicon's physical properties and reduce power consumption. has been done.

As a transistor using a compound semiconductor,
Field-effect transistors have been developed first due to their simple manufacturing process, but as manufacturing processes have progressed, bipolar transistors have also been developed. Superior performance is being realized by

Furthermore, a new device based on an operating principle different from that of conventional transistors has been proposed as an amplification element using a compound semiconductor, and it is expected that excellent possibilities will be realized.

(c) Conventional technology and problems Tunneling hot electron transfer amplifier
The device proposed earlier, named (THETA), is one of the devices that is expected to be realized using compound semiconductors. (M. Heiblum,
IEEE1980Electron Devices Meeting, tech,
digest PP.629-632) Figure 1 is a potential diagram explaining the operating principle of this device proposed above, and Figure 2 is a proposed example of configuring this device using a GaAs-based compound semiconductor. This is a potential diagram. This device has three regions: an emitter, a base, and a collector, and potential barriers are provided between the base, emitter, and collector, respectively.

For example, at a temperature of 77 K, when a bias voltage is applied that makes the emitter a negative potential with respect to the base, electrons forming the emitter current _JEB penetrate the barrier between the emitter and the base due to the tunnel effect. These electrons have approximately the same energy, and in the base region, the potential difference V _EB between the emitter and base causes e to the conduction band edge.
−V _EB is at a higher energy level. Electrons with this energy move elastically toward the collector, but between electrons, between electrons and lattice atoms, and between electrons and electrons.
When the mean free path in the X direction, which is a total of collisions between impurity atoms, is le, the probability that an electron passes through the base region of length d _B is exp(-d _B /le).

When the barrier height on the collector side with respect to the base region is φc, and 1/2 of the normal width of the energy of the electron beam is δ, when the X component of the energy level difference of electrons is larger than φc + δ, Most of the emitter current _JEB can cross the barrier φc on the collector side. Therefore, the loss of electrons in the base region, quantum mechanical reflection and absorption at the base-collector interface, and the region near the barrier interface d ^M _CB
By minimizing the scattering by the lattice atoms and the energy width 2δ of the electron beam, the current ratio α=I _C /I _E can be asymptotic to 1.

The maximum gain of this device is α ² Rout/4Rin,
Increase the collector impedance Rout and decrease the emitter impedance Rin. For this purpose, since φ _C <φ _E , d _CB > d _BE .

The proposal shown in Figure 2 consists of a semiconductor heterojunction structure consisting of an n ⁺ -type GaAs contact layer with a thickness of 1 [μm], an n-type GaAs emitter layer with a thickness of 300 [Å], and a thickness of 80 [Å].
n-type Ga0.6Al0.4As barrier layer, 100 [Å] thick i-type GaAs base layer, 120 [Å] thick n-type
Ga0.8Al0.2As barrier layer, 300 [Å] thick n-type
GaAs collector layer and 1 [μm] thick n ⁺ type GaAs
Consisting of a contact layer, φ _E ≒0.4 [eV],
φc≒0.2 [eV]. Total 900 for this structure
The time it takes for electrons to pass between the emitter layer and collector layer of [Å] is predicted to be about 10 ^-12 seconds.

In order to operate the semiconductor heterojunction structure described above, it is necessary to provide electrodes on the emitter, base, and collector, respectively. The emitter and collector are each of n ⁺ type as shown in Figure 2.
Through the GaAs contact layer, an ohmic contact electrode can be easily provided using a material such as gold/germanium alloy/gold (AuGe/Au).

However, there are problems with the base electrode. That is, the base layer has a thickness in the above proposal.
It is an i-type with a thickness of 100 [Å], and the impurities necessary to realize this device are introduced at as low a concentration as possible, and the thickness is as thin as possible, for example, 100 to 200 [Å], in order to shorten the base transit time of electrons. ] is desirable. It must be said that it is practically impossible to provide an ohmic electrode with low contact resistance on such a thin semiconductor layer with low impurity concentration. In other words, if the impurity concentration is on the order of 10 ¹⁷ [cm ^-3 ], even if the thickness of the semiconductor layer is sufficient,
Even if the optimal conditions for the AuGe/Au-based material composition and alloying heat treatment are selected, the contact resistance remains 1×10 ^-5 [Ωcm ² ].
It becomes more than a certain degree. Furthermore, the thickness of the base layer of the present device does not allow the alloy region to reach the barrier layer or a layer further below, making it impossible to obtain the function of the present device.
If the alloying heat treatment is limited to prevent this alloy region from penetrating the base layer, the contact will become worse.

This problem is thought to be solved if the base electrode as well as the emitter and collector electrodes is provided through a semiconductor layer with a high impurity concentration and the required thickness, and it is possible to realize this device. Therefore, it is desired to establish a manufacturing method.

(d) Object of the Invention It is an object of the present invention to provide a method for manufacturing a base electrode structure for realizing the above-mentioned semiconductor device abbreviated as THETA.

(e) Structure of the Invention The object of the present invention is to provide an emitter layer, a first barrier layer that can be penetrated by an electron tunneling effect, and a base layer made of an n-type or i-type semiconductor on a semiconductor substrate. a layer, a second barrier layer, and a collector layer, and a mask is provided on the layered structure so that the width of each layer on the base layer is reduced by the width of the layer on both sides of the mask. a step of selectively etching to form a pattern that extends outward; and a step of selectively laminating an n-type semiconductor layer in contact with the base layer with a higher impurity concentration than the base layer under the mask using the projecting shape of the mask. The base electrode is grown separately from the structure, and the base electrode is
This is achieved by a method of manufacturing a semiconductor device characterized in that the semiconductor device is provided in contact with a semiconductor layer.

(f) Embodiments of the Invention The present invention will be specifically described below using embodiments with reference to the drawings. FIGS. 3A to 3D are cross-sectional views showing an embodiment of the present invention in the order of steps.

See Figure 3 a. n ⁺ type GaAs with an impurity concentration of about 2×10 ¹⁸ [cm ^-3 ]
Molecular beam epitaxial growth method (hereinafter referred to as
The following semiconductor layers are grown by a metal organic pyrolysis vapor deposition method (hereinafter referred to as MOCVD method) or the like. However, the concentrated composition ratio X below represents the Al composition ratio of AlxGa ₁ -xA _s , and X=0 represents GaAs. Note that each value is 1
Give an example.

^{Sign Composition ratio _ _} 2×10 ¹⁸ 4000 However, the n-type GaAs layer 3 is the collector layer,
The GaAs layer 5 is a base layer, the n-type GaAs layer 7 is an emitter layer, and the non-doped AlGaAs layers 4 and 6 are barrier layers.

Refer to FIG. 3b. Semiconductor layers above the n-type GaAs base layer 5, in this example, the n ⁺ -type GaAs contact layer 8,
n-type GaAs emitter layer 7 and non-doped
The AlGaAs barrier layer 6 is patterned, and selective etching is also performed to expose the base layer 5 in the region where the base electrode is to be provided.

In the present invention, the selective etching mask 9 is made of, for example, silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or aluminum nitride (AlN), since it also serves as a mask for selective epitaxial growth, which will be explained later. The shape and dimensions are such that the width necessary to separate the base contact layer from the emitter layer, etc. is added to the periphery of the required emitter region.

Furthermore, in this etching, the layer 8 made of GaAs is first etched by a gas plasma etching method using an etchant that etches GaAs at a sufficiently higher etching rate than AlGaAs, such as carbon dichloride difluoride (CCl ₂ F ₂ ). and mask 7
The pattern is reduced and etched to the original design value of the emitter area. In this etching process, the gas pressure is first set to a low pressure of, for example, about 0.1 [Pa], and etching is performed faithfully to the pattern of the mask 9 using a strong anisotropic etching effect, and then the gas pressure is reduced to, for example, about 5 [Pa]. By performing side etching with a highly isotropic etching effect, the shape and size of the emitter region after etching can be better controlled.

The non-doped AlGaAs barrier layer 6, which served as a stop layer for the etching process, is etched using, for example, a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O). Therefore, n-type
GaAs base The required etching is completed with almost no wear on the GaAs base layer 5.

Refer to Figure 3c. For example, an impurity concentration of 2
An n ⁺ type GaAs layer 10 having a thickness of ×10 ¹⁸ [cm ^-3 ] and a thickness of about 2000 [Å] is grown to serve as a base collector layer. In most cases, a mask 11 is provided during this epitaxial growth. The mask 11 is made of the above-mentioned heat-resistant material like the mask 9, but the mask 9
and other materials that can be selectively left behind.

When the n-type GaAs layer 10 is grown, it is blocked by the overhang part of the mask 9, so this layer does not grow near the barrier layer 6, etc., and the barrier layer 6 to contact layer 8 and the n-type GaAs base contact are blocked. layer 1
0 is separated.

Note that this epitaxial growth can be performed without depositing GaAs on the masks 9 and 11 by the MOCVD method. Also
GaAs deposited on the masks 9 and 11 by epitaxial growth using the MBE method is in an amorphous or polycrystalline state.

See Figure 3d. Masks 9 and 11 and the deposits on the masks.
If the GaAs layer is present, it is also removed,
A trench 12 for element isolation is formed, for example, with AuGe/
Collector electrode 13 and base electrode 14 using Au
and an emitter electrode 15 are provided. In this embodiment, the base electrode 14 is made of AuGe200 [Å]/Au1000.
[Å]/WSi3000 [Å], and the alloying heat treatment was performed at a temperature of approximately 450 [℃] and for approximately 30 seconds.
The alloyed region remains within the n ⁺ type GaAs layer 10.

As explained above, a base electrode with good low contact resistance was provided according to the present invention, and the sample of this example performed the THETA operation, establishing the basis for future development.

Although the above embodiment uses GaAs/AlGaAs as the semiconductor material, the present invention can be similarly applied to THETA using other semiconductor materials.

(g) Effects of the Invention As explained above, according to the present invention, THETA, which has been proposed as a new high-speed amplification element, can be realized as a semiconductor device, and can be expected to have a promising future as a high-speed semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the operation of THETA, FIG. 2 is an energy diagram showing an example of this device proposed previously, and FIGS. 3 a to 3 d are cross-sectional views in order of steps showing an embodiment of the present invention. In the figure, 1 is an n ⁺ type GaAs substrate, 2, 8 and 10 are n ⁺ type GaAs layers, 3 is an n type GaAs collector layer,
4 and 6 are non-doped AlGaAs barrier layers, 5 is an n-type GaAs base layer, 7 is an n-type GaAs emitter layer,
9 and 11 are masks, 13 is a collector electrode, 14
1 is a base electrode, and 15 is an emitter electrode.

Claims (1)

[Claims] 1. An emitter layer, a first barrier layer through which electrons can penetrate by a tunnel effect, a base layer, and a second barrier layer made of an n-type or i-type semiconductor on a semiconductor substrate. A pattern in which a layered structure is formed having a barrier layer and a collector layer, a mask is provided on the layered structure, and the width of each layer on the base layer is smaller than that of the mask so that both sides of the mask protrude outward. selectively etching an n-type semiconductor layer that is in contact with the base layer at a higher impurity concentration than the base layer from the laminated structure under the mask using the protruding shape of the mask; A method for manufacturing a semiconductor device, characterized in that a base electrode is provided in contact with the highly doped n-type semiconductor layer.