JPH031876B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character and graphic information storage device that can reduce the waiting time of a television teletext receiver.

Journal of the Television Society October 1980 issue (Vol. 34, No.
10), pages 5 to 32, teletext teletext broadcasting is progressing toward realization. In order to facilitate understanding of the present invention, the signal concept of television teletext broadcasting will be simplified and explained within the scope necessary for the present invention. The television teletext signal is defined by the vertical blanking period (VBL) of the television signal.
This is a method in which a pulse-like signal is transmitted to one to several horizontal scanning lines within the horizontal scanning line. A memory is provided on the receiver side, and pulse signals that are intermittently sent within the VBL, that is, with a vertical repetition period of 16.7 mS, are stored in this memory, and character and graphic information is reproduced on the cathode ray tube. The picture elements of one screen are 248 picture elements in the horizontal direction and 204 picture elements in the vertical direction, and the amount of information is 248 x 204 bits or 50592 bits, approximately.
It becomes 51K bits. In addition to this, there is also information such as color information and control information, but the explanation will be omitted since it would be too complicated. The amount of information of approximately 51K bits per screen is
A total of 296 bits, including 248-bit character/graphic pattern information and a 48-bit header section for signal recognition, is sent as one transmission unit (packet) superimposed on one horizontal scanning line. Therefore, the horizontal scanning period is divided into 364 bits,
Of these, 296 bits are allocated as pulse signals.
This bit clock frequency is 5.727272MHz, which is 364 times the horizontal repetition frequency. Therefore, 1
The time to transmit the screen is 248×204/248×16.7ms=3.406(s). If this were to be transferred repeatedly for 8 programs, the maximum waiting time would be 3.4 x 8 = 27.2 (seconds).
It will be 27.2 seconds. (Of course, if you add the color information and control information mentioned above, it will be a little longer.) The above is the signal concept of teletext broadcasting. The following waiting time mitigation measures are explained below.

FIG. 1 is an explanatory diagram of waiting time mitigation measures. In FIG. 1, P1, P2...P8 mean eight types of programs (screens in this case), and _T0 is the repetition period of these eight programs, and is also the maximum waiting time mentioned above. As a measure to alleviate waiting time, it has 8 pieces of memory for approximately 51K bits per screen, and sequentially stores P1 and P2 in this memory.
...If you update P8 every time it is transmitted,
After power-on T ₀ hours, the waiting time is zero. Although this is an effective method, it also requires approximately 51K bits x 8 pieces of memory = 408K bits (51K bytes). Figure 1 shows the memory for alleviating this waiting time.
(hereinafter referred to as buffer memory: BF) for four screens is shown. BF1, BF
2, BF3, and BF4 are the numbers of four buffer memories. As shown in Figure 1, character multiplex signals P1, P2, P3, P are transmitted as P1, P2...P8.
4 are stored sequentially in BF1, BF2, BF3, and BF4, and the next P5 is already stored in P1.
Store it in BF1. Repeating this process, in the example of Figure 1, within the period T _H that is half of T ₀ , P
Since all programs 1 to P8 are stored, the waiting time is less than T _H. In addition, it is only necessary to wait for P5 at the maximum _TH , which means that the maximum waiting time is shortened from T ₀ to _TH .

Next, the problems of this waiting time alleviation measure will be explained using a specific example in FIG. When program P1 is selected at time K in FIG. 1, since P1 is stored in BF1, the character and graphic information of BF1 will be transferred to the display memory, but a time Δt will elapse to prepare for the start of transfer. Suppose that the memory contents of BF1 are transferred to the display memory over time t _R at time x.
However, time x is also the start time when BF1 is rewritten to program P5, and the aforementioned transfer of P1 to the display memory and program update will conflict. When such contention occurs, the same BF1 memory must be read and written at the same time, which is impossible with normal memory driving methods. FIG. 2 is a conceptual diagram of the operation of a method of reading and writing between the display buffer memory and the display memory in a time-sharing manner, that is, the cycle steal method. In Figure 2, t _M is 1 unit for processing, for example
The time is set to about 1μs. During the first half ta time of _tM , the character information signal from the character signal extraction section is
At this time, the display data in the display memory is output. During the second half tb time, data is transferred from the BF memory to the display memory. If we transfer 8 bits of data at the same time using ta and tb,
Data can be transferred in 50592 bits or _6324tM time. Although this time-sharing method apparently allows simultaneous reading and writing, in the event of the above-mentioned conflict, the screens of P1 and P5 will be mixed and transferred from BF1 to the display memory, meaningless The disadvantage is that the information is displayed.

It is an object of the present invention to eliminate the above-mentioned drawbacks of the prior art, and to
To provide a character/graphic information storage device which correctly stores character signal extraction signals in a buffer memory even if the timings overlap.

In order to achieve the above object, the teletext receiver includes a teletext signal extracting means, a plurality of buffer memories, a display memory, and a connection between the teletext multiplex signal extraction means and the plurality of buffers or between the buffer memory and the display memory. A storage transfer control means for controlling the storage transfer control means is provided. And one with buffer memory
If you want to transfer text and graphics information from the text multiplex signal extraction means to a buffer memory that is currently being transferred during the period when text and graphics information is being transferred from the text to the display memory, it is necessary to transfer the text and graphics information to another area of the buffer memory as described above. It is controlled by a storage transfer control means.

The present invention will be explained in detail below with reference to FIGS. 3 to 6.

FIG. 3 is a block diagram showing one embodiment of the present invention. In FIG. 3, 1 is a character signal extraction unit that extracts a character multiplex signal from a television signal; 2
3 is a microprocessor that controls the entire device of this embodiment, that is, an arithmetic control section; 3 is a program storage section that stores the control procedure of the arithmetic control section 2;
5 is a timing generator for generating a timing signal for the entire device; 6 is a working memory in which the arithmetic control unit 2 temporarily stores information for arithmetic control; Department,
7 is a display timing generator that generates a display timing signal for reading out the display memory 15 in synchronization with a television synchronization signal; 8 is a display buffer memory 1;
9 is an 8-bit parallel output signal read from the display memory 15; a parallel-to-serial converter that converts the signal into a temporally serial signal; 16;
1 is a television signal synthesis unit that converts and synthesizes display signals arranged in series in time into a television signal format. Each display buffer memory 10, 11, 12, and 13 each has one display unit, in this case about 51K bits. , 10 is BF1, 11 is BF2, 12 is BF3,
13 corresponds to BF4. 20, 21, 22, 2
Reference numerals 3 and 24 are memories, address switching units that switch address signals supplied to 10, 11, 12, 13, and 15, and 17 is an inverter. Also, 3
2 is a video signal input terminal to which the detection output signal of the television receiver arrives; 31 is a color subcarrier signal input terminal to which the color subcarrier signal of the television receiver arrives; 33
34 is a horizontal synchronization signal input terminal to which the horizontal synchronization signal of the television receiver arrives; 34 is a vertical synchronization signal input terminal to which the vertical synchronization signal of the television receiver arrives; 35 is the
This is a display signal output terminal through which character and graphic information read from the display memory is converted into a television signal and output.

FIG. 4 is a conceptual diagram of the operation of this embodiment. When program P2 is selected at time K in FIG. 4A, BF
2 stores P2, but in the conventional example shown in FIG. 1, BF2 stores program P6 at exactly time (K+Δt).
will be written. In the present invention, the buffer memory to which data is written at this time is changed from BF2 to BF3, BF2 holds program P2 as it is, and text/graphic information is transferred to the display memory. The basic technical idea of the present invention has been described above, and will be explained below using specific circuit operations.

First, extraction of the character multiplex signal and transfer to the buffer memory will be described. In Figure 3, the video signal input terminal 32
A character signal extracting section 1 extracts only a character multiplex signal from the video signal input from the character signal extracting section 1. At this time, when character signal extraction section 1 extracts and holds 296 bits within one horizontal scanning period in VBL, it generates an interrupt on signal path 52 and notifies arithmetic control section 2. Arithmetic control unit 2
immediately generates the address of the character signal extraction unit 1 on the signal path 50 and converts 296 bits into 1 byte (8 bits).
Each time, the signal is taken in by the arithmetic control unit 2 via the signal path 51. In the arithmetic control section, the character/graphic information of the character multiplex signal is sent to the buffer memory 1 via signal paths 50 and 51.
0, 11, 12, 13 (hereinafter BF1, BF2, BF
3, abbreviated as BF4). At this time, as shown in the example of Fig. 4, P1 is transmitted.
For 3.4 seconds, the character multiplex signal from the character signal extraction unit 1 is stored in BF1 (10 in Figure 3), and then the next P
2 for 3.4 seconds, BF2 (11 in Figure 3)...is repeatedly transferred and stored in sequence. Therefore BF1, BF
The storage order of 2, BF3, and BF4 is as shown in FIG. 4A. Also at this time, BF1, BF2, BF3, BF
The program code contained in No. 4 is stored in the working memory 6. For example, at time H in FIG. 4, program codes P1, P2, P3, and P8 are stored in the working memory 6.

Next, a method for transferring character and graphic information from BF1, BF2, BF3, and BF4 to display memory 15 will be described. When a program code desired to be displayed is inputted from the key input section 4, an interrupt is generated to the arithmetic control section 2 via the signal path 52. The arithmetic control section 2 takes in the program code inputted from the key input section 4 via the signal paths 50 and 51 by this interruption and temporarily stores it in the working memory section 6. Subsequently, the arithmetic control section 2 compares the program codes BF1 to BF4 previously stored in the working memory section with the program code input from the key input section just entered. If there is no match, leave it as is, and repeat the comparison every time the program codes BF1 to BF4 are rewritten. On the other hand, if there is a match, the number of the matched BF is transmitted to the memory control unit 8 via signal paths 50 and 51. The memory control section 8 immediately outputs the memory address signal of the BF number given from the arithmetic control section 2 to the signal path 58, and at the same time outputs the writing destination address of the display memory 15 to the signal path 56. Further, a read/write control signal (hereinafter abbreviated as R/W signal) is generated from the signal path 55, and the BF memory side is put into a reading state and the display memory 15 side is put into a writing state.
Then, the character/graphic information is sequentially transferred until the BF memory reaches the final address. When the transfer is completed, the memory control unit 8 generates an interrupt on the signal path 52 to notify the arithmetic control unit 2 of the completion of the transfer.

Next, these BF1 to BF4 and the display memory 15
The timing relationship will be explained. Since the embodiment shown in Fig. 3 also uses the cycle steal method similar to the conventional example shown in Fig. 2, BF1 to BF4 are read and written in time division, and when viewed over a long period of time, the front and back sides are read and written. It can be considered that reading and writing are being performed at the same time. The address switching units 20 to 24 are cycle-steal type time-division changeover switch circuits. For controlling these switches, a timing signal is supplied from the timing generation circuit 5 via a signal path 54. This timing signal is
The timing generation circuit 5 connects the arithmetic control section 2, the display timing section 7, the memory control section 8 and the signal path 5.
9, 60, and 53, and are all synchronized.

FIG. 5 is a diagram showing the operational concept of the cycle steal method.

When any one of BF1 to BF4 is in the period tb in which a character signal from the character signal extraction section is stored, the display memory 15 is in a display period. That is, the address switching units 20 to 24 are connected to b, and the address switching units 20 to 24 are connected to b.
A memory address signal is applied to BF4 from the arithmetic control section 2, and a display memory read address from the display timing generation section is applied to the display memory.
During the next ta period, the address switching sections 20 to 24 are connected to a, and the BF address signal selected from the memory control section 8 through the signal path 58 is transferred to the display memory 1 through the signal path 56 to the BF as described above.
8 address signals are supplied.

FIG. 6 is a conceptual diagram showing a specific example of transferring P6 to BF3 instead of BF2 when P2 is transferred to the display memory at time K in FIG.

In FIG. 6, KB/BF20 is the 20th address in the working memory section 6, a memory area for temporarily storing key inputs, and BF1, 21 is the 21st address in the working memory section 6, which is the program stored in BF1. Area for temporarily storing code, BF2, 22 is BF2, BF3, 23
BF2, BF4, and 24 are areas for temporarily storing the program codes of BF4, and TFG25 is an area for storing a flag indicating that character and graphic information is being transferred from BF to display memory at address 25 in the working memory. POINTER26 is address 26 in the working memory 6, and is an area that stores the memory address containing the program number of the BF currently transferring information from the character signal extraction unit 1, that is, the repetition of 21 to 24 is stored. It is an area. At time L in Figure 6, POINTER
"21" is stored in 26, and the character/figure signal from the character signal extraction section 1 is transferred to BF1.
Next, when a key input P2 is input from the key input section 4 at time P, P2 is temporarily stored in the KB/BF 20 according to the procedure described above. The arithmetic control unit 2 has this P2 from 21 to
Check whether it is within address 24. In the example in Figure 6, it exists at address 22, so TFG
25 to “1” and BF is sent to the memory control unit at time Q.
Supply the first address of 2. Therefore, starting from time Q, the transfer of character and graphic information from BF2 to display memory 8 begins and ends after time _tR . When time K arrives, POINTER26 is changed to 21→22→23→
Go one step forward by repeating 24 → 21 → 22 → 23 → 24,
In other words, it will increase from 21 to 22, but at this time
With reference to the TFG 25, POINTER is controlled so that if it is "0", it advances one step, and if it is "1", it advances two steps. Since it is "1" here, POINTER becomes "23" and the transmission signal P6 is written to BF3. Further, after the t _R time has elapsed, the TFG 25 is returned to "0" by an interrupt from the memory control unit 8 mentioned above. At time Z, since TFG25 is "0", POINTER is only increased by one from 23 to 24.

Looking at the period after time K in Figure 5, we see that BF2 in period tb.
The character and graphic information is transferred from the display memory 15 to the display memory 15.
The character signal P6 from the character signal extraction unit 1 is stored in the BF3 during the ta period, and the display memory 15 is displayed at the same time.

As described above, according to the present invention, character signals can be correctly stored and displayed without causing any inconvenience even if the timing overlaps when transferring character and graphic information from the buffer memory to the display memory in a device that receives character and graphic information. . This also ensures that the character signal waiting time mitigation measures are taken and the performance is improved.

All the controls on the working memory shown in FIG. 6 are performed by the arithmetic control section 2 shown in FIG. 3, that is, the microprocessor.

Also, in Figure 6B, the method is to swap BF2 and BF3 at time K, and in Figure 6, P is used at time K and BF3.
This can be achieved by replacing the data in BF2 and BF3 after writing 6.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a waiting time mitigation measure in the prior art, FIG. 2 is a conceptual diagram of the operation of the cycle steal method in the prior art, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a conceptual diagram of the operation of the embodiment of the present invention, FIG. 5 is a conceptual diagram of the operation of the cycle steal method of the present invention, and FIG. 6 is a diagram explaining the operation of FIG. 3. 10 to 13...Display buffer memory (BF1 to BF
4), 15...display memory, 20-24...address switching unit.

Claims (1)

[Scope of Claims] 1. A device for receiving text and graphics signals of a plurality of programs that are repeatedly transmitted, comprising: a text and graphics signal extracting means for extracting the text and graphics signals; and a temporary storage device for storing the transmitted text and graphics signals for a plurality of programs. storage means; display storage means for storing character and graphic information for display on a display device; control for transferring signals from the character and graphic signal extraction means to the temporary storage means; and a plurality of programs stored in the temporary storage means. and storage and transfer control means for collectively controlling the extraction of character and graphic information of a program to be displayed from the character and graphic signals of the program and transfer to the display and storage means, and the storage and transfer control means is configured to control the temporary storage. a transfer operation of transferring the character/graphic information of the program to be displayed from the storage area thereof to the display/storage means; and a transfer operation of transferring the character/graphic signal from the character/graphic signal extracting means to the storage area of the temporary storage means. A text/graphic information storage device characterized in that, when a transfer operation to be transferred conflicts, the text/graphic signal is transferred to another area of the temporary storage means.