JPH03188619A - Method for heteroepitaxially growing iii-v group compound semiconductor on different kind of substrate - Google Patents
Method for heteroepitaxially growing iii-v group compound semiconductor on different kind of substrateInfo
- Publication number
- JPH03188619A JPH03188619A JP32882189A JP32882189A JPH03188619A JP H03188619 A JPH03188619 A JP H03188619A JP 32882189 A JP32882189 A JP 32882189A JP 32882189 A JP32882189 A JP 32882189A JP H03188619 A JPH03188619 A JP H03188619A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- grow
- substrate
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 21
- 150000001875 compounds Chemical class 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 15
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000470 constituent Substances 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 28
- 238000000137 annealing Methods 0.000 abstract description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 abstract 7
- 229910017214 AsGa Inorganic materials 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 150000001721 carbon Chemical class 0.000 description 1
- 238000004871 chemical beam epitaxy Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は■−v族化合物半導体をSi基板等の異種基板
上にヘテロエピタキシャル成長する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for heteroepitaxially growing a ■-v group compound semiconductor on a heterogeneous substrate such as a Si substrate.
異種基板上への■−V族化合物半導体の成長は、太陽電
池、光電子集積素子等の応用をめざして広く研究されて
いる。この内、基板としてもっとも広く用いられている
Si基板と■−V族化合物半導体との間には、例えばG
aAsにおいては4%、InPにおいては8%の格子不
整合が存在する為に直接これらをSi基板にエピタキシ
ャル成長させることは出来ない。また、熱膨張係数の差
により、反りやクラックが入るという問題もあ。The growth of ■-V group compound semiconductors on heterogeneous substrates has been widely studied with the aim of applying them to solar cells, optoelectronic integrated devices, and the like. Among these, for example, there is a gap between the Si substrate, which is the most widely used substrate, and the ■-V group compound semiconductor.
Since aAs has a lattice mismatch of 4% and InP has a lattice mismatch of 8%, these cannot be epitaxially grown directly on a Si substrate. There is also the problem of warping and cracking due to differences in thermal expansion coefficients.
る、これらの問題点を解決するために一般に種々のバッ
ファ層を導入することが行われている0例えば、G a
A s / S iにおいては、バッファ層上°に成
長するGaAsの成長温度よりも低温で成長させたGa
As (ジャパニーズ ジャーナル オブ アプライド
フィジックス 24巻 843ページ 1984年)
、歪超格子(アプライドフィジックス レターズ 48
巻 1223ベージ 】986年)等がバッファ層とし
て用いられている。また、熱サイクルアニール(アプラ
イドフィジックス レターズ 50巻 31ペ一ジ19
87年)による転位低減効果も報告されている。In order to solve these problems, various buffer layers are generally introduced.For example, Ga
In As/Si, Ga is grown at a lower temperature than the growth temperature of GaAs grown on the buffer layer.
As (Japanese Journal of Applied Physics, Volume 24, Page 843, 1984)
, Strained Superlattice (Applied Physics Letters 48
Volume 1223 Page] 986) etc. are used as a buffer layer. In addition, thermal cycle annealing (Applied Physics Letters, Volume 50, Page 31, Page 19)
1987) has also been reported to have a dislocation reduction effect.
しかしながら、いずれの方法においても依然として■r
−v化合物半導体成長層中には106CI11−’を越
える高密度の残留貫通転位が存在する。However, in either method, ■r
A high density of residual threading dislocations exceeding 106 CI11-' is present in the -v compound semiconductor growth layer.
本発明は貰種基板上に転位の少ないIII−V化合物半
導体をヘテロエピタキシャル成長させる方法を提供する
ことを目的とする。An object of the present invention is to provide a method for heteroepitaxially growing a III-V compound semiconductor with few dislocations on a seed substrate.
本発明のヘテロエピタキシャル成長法は、■V族化合物
半導体成長層を1層または多層のバッファ層を介して当
該成長層以外の異種基板上にヘテロエピタキシャル成長
させる方法に於て、カーボンを高濃度にドーピングした
■−V族化合物半導体で成るバッファ層を成長する工程
を備えていることを特徴としている。The heteroepitaxial growth method of the present invention consists of (1) a method in which a group V compound semiconductor growth layer is heteroepitaxially grown on a substrate of a different type other than the growth layer through one or multiple buffer layers, in which carbon is doped at a high concentration; (2) The method is characterized by a step of growing a buffer layer made of a V-group compound semiconductor.
本発明によるヘテロエピタキシャル成長法では、まずカ
ーボンを高濃度にドーピングした■−■族化合物半導体
バッファ層を基板上に成長させる0例えばカーボンドー
プではGaAs中に10”cm−’以上ドーピングする
ことが可能である。GaAsとSi界面で発生した高濃
度の転位はGaAsバッファ層中でこのカーボンによっ
てピンニングされて消滅する。ここでGaAs中のカー
ボン濃度はホスト原子濃度の数%以上の割合になるため
貫通転位がカーボン不純物に当たる確率が高い、従って
、このバッファ層上に成長したアンドープGaAs層ま
で貫通する転位は減少し、低転位のGaAs成長層が得
られる。また力−ボン不純物は拡散係数が小さいため高
濃度にドーピングされたバッファ層からアンドープ層へ
の拡散も小さいためデバイス応用上も優れている。In the heteroepitaxial growth method according to the present invention, first, a ■-■ group compound semiconductor buffer layer doped with carbon at a high concentration is grown on a substrate. The high concentration of dislocations generated at the interface between GaAs and Si are pinned by this carbon in the GaAs buffer layer and disappear.Here, since the carbon concentration in GaAs is several percent or more of the host atomic concentration, threading dislocations occur. There is a high probability that carbon impurities will hit carbon impurities. Therefore, the number of dislocations penetrating to the undoped GaAs layer grown on this buffer layer is reduced, resulting in a GaAs growth layer with low dislocations.Also, carbon impurities have a small diffusion coefficient, so Diffusion from the heavily doped buffer layer to the undoped layer is also small, making it excellent for device applications.
以下図面を用いて本発明の詳細な説明する。 The present invention will be described in detail below using the drawings.
第1図は本発明の一実施例を説明する成長工程図である
。本実施例では<001>方向に2°オフアングルをつ
けたSi (100)基板11をます900°Cの高温
で熱処理する。これによってアンチフェイズドメイン(
antiphase domains)の発生を抑える
。この基板上にアンドープGaAsバッファ層12を3
00℃で1100n成長させた後、600°Cで15分
間アニールする(第1図(a))、その後450℃でア
ンドープGaAsバッファ層13を1100n成長させ
、次にカーボン(C)を5 X 10 ”am”ドーピ
ングしたGaAsバッファ層14を1μm成長したく第
1図(b))。その後成長温度を500℃にしてアンド
ープGaAs層15を3μm成長させた(第1Cドープ
GaAsバッファ層14の成長にはトリメチルガリウl
x (Ga (CH3)3 )とアルシン(AsH3)
を用い、アンドープGaAs層の成長にはトリエチルガ
リウム(Ga(CzHl)3)とアルシンを用いてこれ
らを切り替えて成長した、本実施例では高濃度のカーボ
ンをドーピングしたGaAsバッファ層により転位が低
減される効果によりエッチビット密度が5X105cm
−’という従来よりも低転位のGaAs成長層が得られ
た。FIG. 1 is a growth process diagram illustrating an embodiment of the present invention. In this example, a Si (100) substrate 11 with a 2° off angle in the <001> direction is heat treated at a high temperature of 900°C. This allows the anti-phase domain (
antiphase domains). Three undoped GaAs buffer layers 12 are formed on this substrate.
After growing 1100 nm at 00° C., annealing at 600° C. for 15 minutes (FIG. 1(a)), then growing an undoped GaAs buffer layer 13 at 450° C. for 1100 nm, and then growing carbon (C) at 5×10 A GaAs buffer layer 14 doped with "am" is grown to a thickness of 1 μm (FIG. 1(b)). Thereafter, the growth temperature was set to 500° C., and an undoped GaAs layer 15 was grown to a thickness of 3 μm (the first C-doped GaAs buffer layer 14 was grown using trimethyl gallium
x (Ga (CH3)3) and arsine (AsH3)
The undoped GaAs layer was grown by switching between triethylgallium (Ga(CzHl)) and arsine. In this example, dislocations were reduced by a GaAs buffer layer doped with a high concentration of carbon. Due to the effect of
-', a GaAs grown layer with lower dislocations than the conventional one was obtained.
上記実施例ではバッファ層及び成長層にケミカルビーム
エピタキシー法を用いたが、有機金属気相成長法、分子
線エピタキシャル成長法等、他の成長法を用いても良い
。In the above embodiment, chemical beam epitaxy was used for the buffer layer and the growth layer, but other growth methods such as organometallic vapor phase epitaxy, molecular beam epitaxial growth, etc. may also be used.
上記実施例ではSi基板上のGaAsの成長について述
べたが、InPの成長にも適用できる。Although the above embodiment describes the growth of GaAs on a Si substrate, the present invention can also be applied to the growth of InP.
その場合には上記のようにSi基板上にGaAsを成長
した後、そのGaAs上にカーボンを高濃度ドーピング
したInPをGaAsとInPとのバッファ層として挟
み込めば良い。In that case, after growing GaAs on the Si substrate as described above, InP doped with a high concentration of carbon may be sandwiched on the GaAs as a buffer layer between GaAs and InP.
上記実施例では熱サイクルアニールは行っていないが、
この手法も組み合わせて用いても勿論良い
上記実施例では歪超格子バッファ層は用いていないがこ
のバッファ層を同時に用いても勿論良い
上記実施例では不純物としてカーボンをドーピングした
が、他の不純物、例えばシリコン(St)とカーボンを
同時にドーピングしても良い。Although thermal cycle annealing was not performed in the above examples,
Of course, these methods can also be used in combination. Although the strained superlattice buffer layer is not used in the above embodiment, it is of course possible to use this buffer layer at the same time. In the above embodiment, carbon is doped as an impurity, but other impurities, For example, silicon (St) and carbon may be doped simultaneously.
本発明によるエピタキシャル成長法は高濃度のカーボン
をI[I−V族化合物半導体にドーピングしたバッファ
層を形成することにより、格子不整合、熱膨張係数の違
いによる転位を不純物原子がピンニングする効果により
、異種基板上に成長した■−■族化合物半導体において
低転位のものが得られる。In the epitaxial growth method according to the present invention, by forming a buffer layer in which a high concentration of carbon is doped into an I[IV group compound semiconductor, impurity atoms have the effect of pinning dislocations caused by lattice mismatch and differences in thermal expansion coefficients. Low dislocations can be obtained in the ■-■ group compound semiconductor grown on a heterogeneous substrate.
第1図は本発明の一実施例であるSi上のGaAs成長
の工程概略図である。図に於て、11・・・<001>
方向に2°オフした5i(100)基板、12・・・低
温成長アンドープGaAs層、13・・・アンドープG
aAs層、14・・・カーボンドープGaAs層、15
・・・アンドープGaAs層長層をそれぞれ示す。
人埋人弁理上内厚 晋
(α)
(b)
閉jFIG. 1 is a schematic diagram of the process of growing GaAs on Si according to an embodiment of the present invention. In the figure, 11...<001>
5i (100) substrate 2° off in the direction, 12...low temperature grown undoped GaAs layer, 13... undoped G
aAs layer, 14... carbon-doped GaAs layer, 15
. . . each shows a long undoped GaAs layer. Atsushi Atsushi (α) (b) Closed J
Claims (1)
異種基板上に1層または複数層のバッファ層を成長し、
当該バッファ層上にIII−V族化合物半導体をヘテロエ
ピタキシャル成長させる方法に於て、カーボンを高濃度
にドーピングしたIII−V族化合物半導体で成るバッフ
ァ層を成長する工程を備えていることを特徴とする異種
基板上へのIII−V族化合物半導体のヘテロエピタキシ
ャル成長法。Growing one or more buffer layers on a heterogeneous substrate made of constituent elements other than the III-V compound semiconductor growth layer,
The method for heteroepitaxially growing a III-V compound semiconductor on the buffer layer is characterized by the step of growing a buffer layer made of a III-V compound semiconductor doped with carbon at a high concentration. A method for heteroepitaxial growth of III-V compound semiconductors on heterogeneous substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32882189A JPH03188619A (en) | 1989-12-18 | 1989-12-18 | Method for heteroepitaxially growing iii-v group compound semiconductor on different kind of substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32882189A JPH03188619A (en) | 1989-12-18 | 1989-12-18 | Method for heteroepitaxially growing iii-v group compound semiconductor on different kind of substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03188619A true JPH03188619A (en) | 1991-08-16 |
Family
ID=18214468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32882189A Pending JPH03188619A (en) | 1989-12-18 | 1989-12-18 | Method for heteroepitaxially growing iii-v group compound semiconductor on different kind of substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03188619A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003015141A1 (en) * | 2001-08-06 | 2003-02-20 | Motorola, Inc. | Controlling anti-phase domains in semiconductor structures |
| JP2003101149A (en) * | 2001-09-19 | 2003-04-04 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| US6855992B2 (en) | 2001-07-24 | 2005-02-15 | Motorola Inc. | Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same |
| US6885065B2 (en) | 2002-11-20 | 2005-04-26 | Freescale Semiconductor, Inc. | Ferromagnetic semiconductor structure and method for forming the same |
| US6916717B2 (en) | 2002-05-03 | 2005-07-12 | Motorola, Inc. | Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate |
| US6992321B2 (en) | 2001-07-13 | 2006-01-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials |
| US7005717B2 (en) | 2000-05-31 | 2006-02-28 | Freescale Semiconductor, Inc. | Semiconductor device and method |
| US7020374B2 (en) | 2003-02-03 | 2006-03-28 | Freescale Semiconductor, Inc. | Optical waveguide structure and method for fabricating the same |
| US7019332B2 (en) | 2001-07-20 | 2006-03-28 | Freescale Semiconductor, Inc. | Fabrication of a wavelength locker within a semiconductor structure |
| US7045815B2 (en) | 2001-04-02 | 2006-05-16 | Freescale Semiconductor, Inc. | Semiconductor structure exhibiting reduced leakage current and method of fabricating same |
| US7067856B2 (en) | 2000-02-10 | 2006-06-27 | Freescale Semiconductor, Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
| US7105866B2 (en) | 2000-07-24 | 2006-09-12 | Freescale Semiconductor, Inc. | Heterojunction tunneling diodes and process for fabricating same |
| US7161227B2 (en) | 2001-08-14 | 2007-01-09 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices for detecting an object |
| US7169619B2 (en) | 2002-11-19 | 2007-01-30 | Freescale Semiconductor, Inc. | Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process |
| US7211852B2 (en) | 2001-01-19 | 2007-05-01 | Freescale Semiconductor, Inc. | Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate |
| US7342276B2 (en) | 2001-10-17 | 2008-03-11 | Freescale Semiconductor, Inc. | Method and apparatus utilizing monocrystalline insulator |
| JP2009514252A (en) * | 2005-11-01 | 2009-04-02 | マサチューセッツ・インスティテュート・オブ・テクノロジー | Monolithically integrated semiconductor materials and devices |
-
1989
- 1989-12-18 JP JP32882189A patent/JPH03188619A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7067856B2 (en) | 2000-02-10 | 2006-06-27 | Freescale Semiconductor, Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
| US7005717B2 (en) | 2000-05-31 | 2006-02-28 | Freescale Semiconductor, Inc. | Semiconductor device and method |
| US7105866B2 (en) | 2000-07-24 | 2006-09-12 | Freescale Semiconductor, Inc. | Heterojunction tunneling diodes and process for fabricating same |
| US7211852B2 (en) | 2001-01-19 | 2007-05-01 | Freescale Semiconductor, Inc. | Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate |
| US7045815B2 (en) | 2001-04-02 | 2006-05-16 | Freescale Semiconductor, Inc. | Semiconductor structure exhibiting reduced leakage current and method of fabricating same |
| US6992321B2 (en) | 2001-07-13 | 2006-01-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials |
| US7019332B2 (en) | 2001-07-20 | 2006-03-28 | Freescale Semiconductor, Inc. | Fabrication of a wavelength locker within a semiconductor structure |
| US6855992B2 (en) | 2001-07-24 | 2005-02-15 | Motorola Inc. | Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same |
| WO2003015141A1 (en) * | 2001-08-06 | 2003-02-20 | Motorola, Inc. | Controlling anti-phase domains in semiconductor structures |
| US7161227B2 (en) | 2001-08-14 | 2007-01-09 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices for detecting an object |
| JP2003101149A (en) * | 2001-09-19 | 2003-04-04 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| US7342276B2 (en) | 2001-10-17 | 2008-03-11 | Freescale Semiconductor, Inc. | Method and apparatus utilizing monocrystalline insulator |
| US6916717B2 (en) | 2002-05-03 | 2005-07-12 | Motorola, Inc. | Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate |
| US7169619B2 (en) | 2002-11-19 | 2007-01-30 | Freescale Semiconductor, Inc. | Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process |
| US6885065B2 (en) | 2002-11-20 | 2005-04-26 | Freescale Semiconductor, Inc. | Ferromagnetic semiconductor structure and method for forming the same |
| US7020374B2 (en) | 2003-02-03 | 2006-03-28 | Freescale Semiconductor, Inc. | Optical waveguide structure and method for fabricating the same |
| JP2009514252A (en) * | 2005-11-01 | 2009-04-02 | マサチューセッツ・インスティテュート・オブ・テクノロジー | Monolithically integrated semiconductor materials and devices |
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