JPH03189734A - Cpu device containing plural memory elements - Google Patents

Abstract

PURPOSE:To prevent such a case where a CPU runs away with abnormality of a certain memory element and damages other memory elements by storing previously a prescribed instruction to the head address of each memory element. CONSTITUTION:A program is described to each memory element of a ROM 2 and a RAM except a ROM 1 serving as a memory element including a program start address at and after the head address of each memory element. When the ROM 1 has no operation at all, the program is carried out at the head address of the ROM 2 while passing through the address of the ROM 1. In this case, the program run is stopped at the head address of the ROM 2 where a program is already described. Thus no damage is given to the RAM nor a system. An exactly same operation is carried out even with no actuation of the ROM 2. Thus it is possible to reduce the probability to rewrite other memories or to damage the system.

Description

DETAILED DESCRIPTION OF THE INVENTION (Fl) Industrial Application Field The present invention relates to a CPU device having a plurality of memory elements.

(bl) Prior Art In conventional CPU devices such as controllers having multiple memory elements (ROM, RAM, etc.), no measures have been taken to guarantee against RAM data destruction or damage to the system in the event of a memory abnormality. As a controller, for example, one having a configuration as shown in Fig. 3 can be considered.The system of this controller includes a CPU, a ROM1
．． ROM2. Consists of RAM, Ilo, and select circuit.
RAM is backed up by a battery. FIG. 4 shows the memory map of this system. Now, suppose that the ROMI stops working at all due to static electricity or mishandling. Then, the ROMI area 0
0001 (address (program start address) to 3FF
The contents of the FH address are all 00. In the case of many CPUs, since 00 is a NOP instruction, the CPU executes the program at the first address of ROM2 without processing anything. Since this is not a normal operation, processing that is different from the programmer's intention will be executed. In other words, incorrect data may be written to the RAM, or the CPU may run out of control, damaging the system. Also, if the same thing happens with ROM2, the contents of RAM are often data, so the CPU treats the data as part of the program and runs out of control, rewriting the contents of RAM. or damage the system. Furthermore, if the contents of the memory are incorrect or there is a mistake in inserting the memory socket, the program instructions will become completely meaningless, and in this case, the CPU will go out of control and overwrite the contents of the RAM. destroy or damage the system.

(C1 Problem to be solved by the invention) As described above, in the past, no countermeasures were taken when an abnormality occurred in some of the multiple memory elements.
There is a problem in that when some memory elements are abnormal, the CPU goes out of control and changes the contents of other memories, causing damage to the system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CPU device that can solve the above-mentioned inconvenience by storing a predetermined instruction in the first address of each memory element in advance.

(d) Means for Solving the Problems This invention provides that in a CPU device having a plurality of memory elements, each memory element except the memory element containing the program start address is arranged starting from the first address (longest instruction byte number of the CPU -
1) It is characterized by being composed of a memory element that stores in advance at least one NOP command and its successor (stop processing program).

(Q) Effect In this invention, if some memory element has an abnormality such as electrostatic damage or incorrect insertion, the CPLI will respond to that memory element at the first address of the memory element that has a higher address space area. Stops with a very high probability. In other words, if memory data is corrupted or a memory socket is incorrectly inserted, there is a very high probability that the CPU will execute the program at the first address of the next memory element while performing random arithmetic processing. Therefore, no matter how long the data at the last address of the memory element in the abnormal state is part of an instruction, the NOP instruction is executed from the next address, which is the first address of the next memory element. Because (CPU's longest instruction pie!・number - 1) instructions are consecutive, the instruction to which the data at the final address corresponds is not executed, passes through the NOP instruction, and becomes the next instruction after the last NOP instruction. The program stops by executing the stop processing program.

By stopping the program, the CPU can reduce the probability of rewriting other memories and damaging the system.

(f) Embodiment FIG. 1 shows a memory map of an embodiment of the present invention. The controller is the same as shown in FIG. As shown in the figure, a program (2) is written in each memory element of ROM2 and RAM except for ROMI, which is a memory element containing a program start address, starting from the first address.

In addition, in this embodiment, an internal RAM is also arranged in the CPU, and this CPU internal [? Program ■ is also written starting from the first address of AM.

Figure 2 shows the contents of the above program ■.Program ■ has N NOP instructions and 'E<JLI
It consists of an infinite routine including MP instructions. In the infinite routine, the JUMP instruction causes the program to jump to the previous address, so the program essentially stops at this position. Note that it is also possible to insert a HALT command instead of this routine. Above N
With NOP instructions, the CPU does nothing, but with NOP instructions, the CPU
is set equal to the number of bytes of the longest instruction in - a number greater than or equal to 1.

With this configuration, if one of the memory elements is abnormal, the CPU operates as follows.

First, if ROMI does not operate at all, the program is executed from the first address of ROM2, bypassing the ROMI address. At this time, since the program (2) is written starting from the first address of the ROM2, the program will not stop there and cause damage to the RAM or the system.

The same applies when ROM2 does not operate.

Next, if the contents of the memory are incorrect or the memory
Consider a case where the CPU goes out of control due to an insertion error. - Approximately 80% of the instruction codes of the CPU are arithmetic instructions, approximately 10% are other processing instructions, and approximately 10% are jump instructions. Further, it is rare that a program is stored until after the address H of the memory element, and the remaining portion is almost always filled with OO or FF. Therefore, if the CPU goes out of control, there is an extremely high probability that the CPU will execute the first address of the next memory element while performing random arithmetic processing. That is, since program (2) will be executed, it is possible to stop the CPU from running out of control at this position. As mentioned above, program ■ has a number (N) of NOP instructions that is greater than or equal to (the number of bytes of the longest instruction - 1), so even if the instruction immediately before executing program ■ is the longest instruction, In the end, nothing was done,
The program is substantially stopped by executing the next stop processing program.

(A) Effects of the Invention According to the present invention, if any of the plurality of memory elements is inserted in the wrong direction or data is destroyed due to static electricity or mishandling, the CPU It is possible to minimize the damage caused to the entire system by destroying the contents of other memory elements by continuing to run out of control.Furthermore, even if memory data may be changed due to external noise, the present invention According to , damage to the system can be minimized.For this reason, devices with noise sources that generate spike noise, especially when the power is turned on, such as halogen lamps, etc.
By using the present invention in an electrophotographic copying machine that has a large number of high-voltage chargers, power switch relays, etc., there is an advantage that recovery work in the event of CPU runaway becomes easier.

[Brief explanation of drawings]

FIG. 1 shows a memory map of an embodiment of the present invention, and FIG. 2 shows the contents of a program located below the first address of a memory element. 3 is a block diagram of a controller to which the present invention is applied, and FIG. 4 is a diagram showing a memory map of a conventional controller. Program - Stop processing program. Figure 1

Claims (1)

[Claims] (1) In a CPU device having multiple memory elements, each memory element except the memory element containing the program start address is
1) A CPU device having a plurality of memory elements, characterized in that it is constituted by a memory element in which at least one NOP instruction and a subsequent stop processing program are stored in advance.