JPH03189868A - Data processor - Google Patents

Abstract

PURPOSE:To accelerate data processing by providing two address buses and data buses to be connected to external memories, respectively, and connecting two external memories in parallel. CONSTITUTION:The data processor 1 contains two registers 2, 3 for multiplica tion, a floating point multiplier 4, a data register group 5, and an arithmetic and logic computing element 6, and couples them in pipeline constitution, and performs parallel processing by performing the same arithmetic operation on a large amount of data successively. The data buses 7, 8, the registers 2, 3 for multiplication, and the data register group 5 are connected mutually, and also, the data bus 7 is connected to the external memory 9, and the data bus 8 on one side is connected to a separate external memory 10. Address values to designate the addresses of the external memories 9, 10 are transmitted from an address arithmetic part 13 to the external memories 9, 10, however, the two address buses 11, 12 are provided, and they are connected to the external memories 9, 10 separately. Thereby, the number of steps of the arithmetic processing can be reduced, which accelerates data processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing processor, and particularly to a data processing processor with improved data processing efficiency.

[Conventional technology 1 A conventional data processing processor that handles digital signals is
Generally, it has a built-in multiplier, arithmetic and logic unit, and internal memory.
Since these have a Vibrine-like data flow configuration, product-sum operations can be performed at high speed by Vibrine-like parallel processing.

Another feature is that the program memory and data memory are separated from the data processor, and a separate address bus and data bus are provided, respectively, so that instruction reading and data transfer can be performed independently.

Therefore, data processing processors are widely used in fields such as signal processing, image processing, neural networks, and the like, where sum-of-products operations are performed on large amounts of data.

[Problems to be Solved by the Invention] In fields such as those requiring product-sum operations on data of the above-mentioned size 11, there is a demand for even faster data processing because the amount of data to be handled is enormous.

Therefore, a technical problem arises that needs to be solved in order to shorten the time required for data transfer, improve the efficiency of calculation time, and speed up data processing, and the present invention solves this problem. The purpose is to

[Means for Solving the Problems] The present invention has been proposed to achieve the above object, and is a processor incorporating a multiplier and an arithmetic and logic unit, which transfers data from an external memory to an internal register. In a processor having a data processing function of reading the data, performing predetermined multiplications and arithmetic and logical operations on the data, and writing the operation results to the external memory, an address bus and a data bus connected to the external memory are connected to each other. It is an object of the present invention to provide a data processing processor characterized by having two external memories connected in parallel.

[Function] In this invention, the external memory is divided into two groups, and address buses and two data paths corresponding to each external memory are separately provided.
g, or two types of data can be transferred simultaneously between internal registers.

Therefore, two pieces of data required by the multiplier or arithmetic unit are read from the external memory at the same time. Further, while data necessary for an operation is read using one data bus, other operation results calculated by parallel processing can be written to an external memory using the other data bus.

[Example] An example of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of a data processor (+). The data processing processor (1) includes two multiplication registers (2) (3), a floating point multiplier (4), a data register group (5), and an arithmetic and logic unit (
6) and are connected in a vibe line configuration as shown in the same figure, so that the same operation can be performed on a large number of data in succession and processed in parallel. Then, the data bus (η(8)), the multiplication registers (2), (3), and the data register group (5) are connected, and the data bus (7)
is connected to external memory (9), and one data bus (8)
is connected to a separate external memory card 10).

Then, the address value for specifying the address of the external memory (9) (In) is transmitted from the address calculation unit (+3) to the external memory (9) (10), but the address bus (I1)
(Two U-rings are provided and each is connected to the external memory (Q) and Qo) separately. Further, the program of the data processing processor (1) is stored in the program memory (1), and each instruction is read and interpreted by the control circuit unit (1!9) to generate a control signal.

With the above pipeline configuration, this data processing processor (1) is configured to: ■ External memory 1 (Q) (lr9 to multiplication register (2)
) (3) ■ Multiplying the data stored in the multiplication registers (2) and (3) and storing the multiplication results in the data register group (5)■ Storing the data in the delta register group (5) The arithmetic and logic unit (6) performs an operation on the existing data, and processes beyond storing the operation result in the data register group (5) can be executed simultaneously. Also, since the two external memory buses 1 and 9) (u'6) are connected by separate data buses (7) and (8),
Instead of (2) above, reading data from one external memory and writing data to the other external memory can be executed simultaneously with (2) above.

For example, a numerical string (alt82+...
...an), numerical string (b,
, b2, ..., bn) are stored in order, and when performing the product-sum operation X=Σ m+'ll+ i=1 of both numbers, two data buses (7) (8 ) to the multiplication registers (2) and (3).
can be read simultaneously. Then, if this data reading, multiplication, and cumulative addition are executed in parallel, Table 1
As shown in the figure, the product-sum operation is completed in n+3 steps.

If there is one data bus, read the numerical value by a,
Since it takes two steps, the number of steps is bn+3.

Also, a numerical string (aIsa2+...) is stored in the external memory (9).
・・a. ), numerical strings (bl, b2 .
. . . b, ) are stored in order, calculate the product of both numerical values, add a constant, and store the result in external memory 0 [0 [0]. Calculation Ci = 3. @ bl +d (+ = 19 2
1 ""n), as shown in Attached Table 2, if the reading of the two numerical values a, , b, and the multiplication and addition are performed in parallel in eveline manner, the number of steps in the arithmetic processing is n+1. Since n steps are required to store the data, the calculation is completed after a total of 20+1 steps.

In a system with one data bus, the numerical values a1 and 2 cannot be read in one step, but require two steps, so bn+
Requires one step.

Then, write the numerical string (al+ a2+
・・・・・・、a. ) and (CI r c,, l...
...Co) is stored and the numerical string (bl, b2゜..., bn) is stored in order in the other external memory 00), calculate the product of al and bl. ,
Furthermore, add 01 to the result and sequentially write the external memory 1 bar 10)
The operation to be stored in d1-ai ” bl + CL
When you execute (1”” L 2+ “’-”n), Attached Table 3
As shown in , reading, multiplication, and addition of two numbers ab and 2 and reading and storing data of number C are performed simultaneously using two data buses (7) and (8), so bn+
The calculation is completed in two steps.

If there is one data bus, three steps are required to read out the numerical value ab c and one step is required to store the data, so bn+2 steps are required to complete the calculation. In this way, by providing two data buses, the data processing speed has been increased by 1.5 to 2 times.

[Effect of the Invention J] As described in detail in the above-mentioned embodiment, this invention allows two pieces of data to be transferred simultaneously between an external memory and an internal register or between internal registers, so the number of steps in arithmetic processing is significantly reduced. The calculation speed is 1.5 to 2 times that of the conventional method.

Therefore, the data processing speed is dramatically increased, and it is possible to contribute to improving the processing efficiency of sum-of-products operations using large HL data, which are frequently performed in signal processing, image processing, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the data processing processor of the present invention. (1) Data processing processor (2) (3)
...Multiplication register (4) ...t7 Dynamic point multiplier (5) ...Data register group (6) ... Arithmetic logic unit (7 )(8)・・・Data bus

Claims (1)

[Claims] A processor incorporating a multiplier and an arithmetic and logic unit, which reads data from an external memory into an internal register, performs predetermined multiplication and arithmetic and logic operations on the data, and writes the result of the operation to the external memory. 1. A data processing processor having a data processing function, characterized in that two address buses and two data buses are provided to connect to external memories, and two external memories are connected in parallel.