JPH0319175A - Data encoding circuit - Google Patents

Abstract

PURPOSE:To eliminate a correction-only delay memory by constituting a shuffling memory by means of at least three blocks so as to correct the difference of recording phase by means of delaying a read timing from one side of memories. CONSTITUTION:The shuffling memory is constituted by at least three blocks (sector memories MA1-MA3 or MB1-MB3), and the read timing from at least one side of the memories MB1-MB3 is delayed compared to the read timing of the other side of the memories MA1-MA3 so as to correct the difference of the recording phase among recording channels. Thus, the need of providing the delay memory for correcting the difference of the recording phase is eliminat ed by correcting the difference of the recording phase based on the difference of the position of inter-recording head for respective recording channels by the same memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data encoding circuit used in an encoder circuit of a digital VTR (video tape recorder), etc. (Summary of the Invention) The present invention provides a data code that distributes an input digital signal for l fields to at least two recording channels, divides it into a predetermined number of recording blocks, and shuffles the divided signal to block encode it. The writing circuit uses at least three blocks of memory for shuffling, and corrects the recording phase difference between the recording channels by delaying the timing of reading from the memory of one recording channel. In addition to expanding the time margin for loading and reading, and expanding the allowable phase shift between the input video signal and the recording reference signal, the recording phase difference based on the difference in position between the recording heads for each recording channel is also increased. The correction is performed using memory. [Prior technology] Digital VT that digitizes and records video signals.
R (video tape recorder) formats include the so-called DI format, which digitizes the combination of luminance signals and chroma signals, NTSC and P
The so-called D2 format, etc., which directly digitizes a composite signal of a television standard system such as AL, is known. In the formants of these digital VTRs, an input digital signal for one field is divided into a predetermined number of blocks, and the divided signals are subjected to so-called shuffling or the like to be block coded. For example, FIG. 4 shows a data encoding circuit, a so-called encoder circuit, on the recording side of the so-called D2 format digital VTR. In this FIG.
After the valid data in I1) is shuffled, it is sent to the outer ECC encoder (or outer parity addition circuit) 13. For example, in the case of so-called PAL method 2, 948 samples are extracted as valid data within IH = 64 μsec of 7, as shown in Fig. 5, and after performing the above-mentioned intra-line shuffling, the AUC ECC encoder I am sending it to l3. The word length of each sample data is 8 bits (1 byte). In addition, the so-called NTSC
In the case of the IH method, as shown in parentheses in the figure,
= 63.55 μSec, and the number of valid data is 768 samples. The numerical values in the following explanation are for the PAL system, and the numbers for the NTSC system are shown in parentheses.

The outer ECC encoder 13 sends the shuffled valid data to two channels, namely channel 0.
and channel l, 474 of each channel
(384) Divide each byte of data into 6 equal parts, 79
(64) Generate six outer parity blocks in which a 4-byte outer parity code is added to the byte data, and output the data DPA and DPB shown in FIG. These output data A and DPB are sent to the sector shuffle circuit 14,
Data for 1 sector 76 (85) lines is written to/read from the shuffle memory, thereby performing sector shuffling. Here, FIG. 6 shows valid data within one field, and the sample data of 304 (255) lines with 948 (768) samples per line is so-called that the sample data is alternately arranged and reversed between lines. It is distributed into channel 0 and channel l in a checkerboard pattern. Also, the valid data in the l field is 76
(85) Each line is divided into four (3) segments, and channel O and channel 1 of each segment constitute a sector. That is, l sector is l
474 (384) per line, 76 (384) in sample file (
85) Since it is a line, the number of sample words or bytes per sector is 474 x 76 = 36024
(Hoot or Neut) :PAL(
384X85=32640 (foot or bite): NTSC). FIG. 7 shows the state of data arrangement within one sector when writing to/reading from one sector memory provided in the sector shuffle circuit 14. That is, first, 474 per line
(384) By distributing the word to the six outer parity blocks, j is asked 474 (384) +6 = 79(
64) By adding a 4-word outer parity code to each block of words and performing this for the above 76 (85) lines, 76 (85) x 6 =
456 (510) bytes, 79 (64) + vertically
4 constitutes a capacity space of 83 (6B) words. The data within each line is rearranged (shuffled) at 12 sample periods. Six sub-arrays (small arrays) each having a height of 76 (85) are arranged in the horizontal direction of this sector array, and when recording data, they are sequentially read out horizontally from the lower left corner in the figure. ) 8 words-8 heights inner ECC for each sup-array of bytes (
Inner parity bow) is added. At this time, as shown in FIG. 7, SYNC (
A synchronization pattern) and an ID (identification pattern) are added to constitute one sync block. Note that the first parity block in the first block block also includes the above-mentioned ID (identification pattern).

Returning again to FIG. 4, the sector shuffle circuit 14 has four sector memories old 1, 182, MB 1, MB.
2 is provided, and from the outer ECC encoder l3,
The sample data distributed to the channels O and I are transmitted through the switching switches SAI and SBI in the sector shuffle circuit 14 to the sector memories MAL, MA2 and ?, respectively. It is sent to IB 1 and MB2, respectively. Figure 8 shows these four sector memories MA.
The writing (W) and read (R) tying for 1-MB 2 is shown for the case of the above PAL system, and two memories of one channel, for example, MAL,
MA2 is controlled so that while data for the above l sectors is written to one side, it is read from the other side.
Channel 0 data read from sector memories MAI, MA2 is output via changeover switch SA2,
Further, the data of channel l read from sector memories MBI and MB2 is outputted via changeover switch SR2. Here, the data write operation to the sector shuffle circuit l4 is performed using the input video signal V in from the input terminal l1.
The data read operation is controlled by a write control signal etc. generated by the timing generation circuit 3l based on the synchronization signal etc. of the timing generation circuit 33 based on the recording reference signal supplied via the input terminal 32. It is controlled by a generated read control signal and the like. this is,
Considering that the recording data is output at the same timing as read from the sector shuffle circuit l4, this is made to match the recording reference signal. Each data of the channels 0 and 1 from the sector full circuit 14 is sent to SYNC, 10, inner ECC addition circuit 16A,
It is sent to 16B. The output data from these additional circuits 16A and 16B is outputted to two parity block blocks, SYNC (synchronization pattern) and 1, as shown in FIG.
The basic unit is a zinc prong with a 0 (identification pattern) added thereto, and a plurality of zinc prongs come together to form a video sector. Audio data, which will be described later, is added to the front and back positions of this video sector, forming recorded data DA and DB for each channel as shown in FIGS. 8 and 9. And one SYNC, [D, {ntEc
The recording data DA from the c-additional circuit 16A is subjected to random encoding by the random encoding circuit +8A and taken out from the output terminal 19A, and the recording data D B +. After the delayed data DDB is delayed by a phase difference of the recording hand, which will be described later, in the t delay circuit l7, it is channel-encoded in the channel-less encoding circuit 18l3 and taken out from the output terminal 19B.

The recording timing signal from the timing generation circuit 33 is
The signal is taken out directly through the output terminal 34A, and through the delay circuit 17 and then through the output terminal 34B. As the basic pulse of this timing signal, for example, the segment pulse SP shown in FIG. 9 can be considered. This segment pulse Sl) is a henodic switching timing pulse for forming the helical trunk, and has a period of 1/4 of the l field in the case of the PAL system (l/3 of the l field in the NTSC system). have.

The recording signal taken out from the output terminal 19A is the first
The record of the rotary hend shank shown in Figure 0 is in the henoto HA, HC.
Further, the recording signal taken out from the output terminal 19B is sent to recording nodes IIB and HD. Here, the recording head HAjlB is at approximately the same position, and the recording head l{C
, HD are arranged in approximately rotating positions, and these heads pair HA, 11 B,:! : Hesoto pairs HC and IID are arranged with an angular difference of 180 degrees on a rotating drum 1 rotating in the direction of arrow r, and a magnetic tape 2 is wound around the circumference of the rotating drum L within an angular range of approximately 180 degrees. arrow (
One of the pairs of heads comes into sliding contact with the magnetic tape 2 every half rotation of the rotating tram l.

From this, the recording signal from the above output terminal +9A is
Every half rotation of the rotating drum l, the recording heads HA and HC are switched to the side that makes sliding contact with the n-air tape 2, and the recording signal from the output terminal 19B is sent to the magnetic tape in the recording heads HB and ID. The feed is switched every half rotation of the rotary drum l to the side that makes sliding contact with the drum l. At this time, the recording head fl
A and HB (or recording heads HC and HD) record and form a pair of helical trunks TA and TB (or TC and TD) on the magnetic tape 2 at the same timing, as shown in FIG. Note that in the PAL system, the I field video signal is recorded on 4 pairs (8 helical tracks), whereas in the NTSC system, the I field is recorded on 3 pairs (6) helical tracks. It has become so.

By the way, since the recording heads HA and HB (or recording heads HC and 11D) of channels O and 1 cannot be physically arranged at the same position, a predetermined angle difference (for example, 4.22 degrees) (and They are arranged with a height difference of 7 degrees (not shown). This results in a drum rotation phase difference between the recording heads HA and +IB (or IC and HD) when performing a recording operation, and is manifested as a shift in the start timing of the tape sliding contact, that is, a shift in the recording timing. Therefore, with respect to the recording signal of the channel O supplied to the recording head HA (HC), the recording signal of the channel] supplied to the recording head HB (HD) is changed to the above drum rotation phase difference C.
By delaying this by a corresponding predetermined time, the discrepancy in the recording timing based on the rotational phase difference between the respective drives is corrected. Next, for the audio signal, the sampling frequency is 48kHz, and the length of one sample word is 2.
0 bit, and per audio sector, PA
In the L system, four channels of audio signals of 240 samples (266 or 267 samples in the NTSC system, hereinafter the numerical values for the NTSC system are shown in parentheses) are supplied to the input terminal 2l in FIG. This input audio signal AU. ．． , the byte conversion circuit 22 performs conversion to allocate 5 words of 8 bits to the 2 samples of 20 bits, and the next AUX data addition circuit 23 adds auxiliary Allκ data. Been 1
This results in 608 (680) bytes of data per audio sector.

The outer ECC adding circuit 24 generates 76 (85) outer parity blocks in which a 4-byte outer parity code is added to 8-byte data. The next audio shuffle circuit 25 performs sector shuffling by writing one sector of the outer parity block into the shuffle memory and then reading it out. Therefore, the data written to the audio shuffle memory is (8+4) x 76 x 4 = 3648 C bytes):PAL((8+4)xssx 4 -
4080 (ノ;ito):NTSC). The audio shuffle circuit 25 outputs 4 sectors of audio data AUO to each channel O and channel I at each timing according to the formant shown in FIG.
A11, A[+2, A[l3] are read out, and the above SYNC
, 10. It is sent to the inner ECC addition circuit +6A and 16B. Note that each of the audio data AIIO to AU3 is written in duplicate, and for example, the audio data ALIO,^υl in the area sent to the hesode HA of the recorded data of the channel O shown in FIG. Audio data ADO, A of the recorded data of
It is the same as ll. Therefore, the recording track corresponding to the l segment of the audio signal and the video signal is as shown by the hatched area in FIG. 11, where the audio data in the four sectors at the top end of the tape is the first copy, and the bottom end is the second copy.

[Problems to be Solved by the Invention] By the way, the timing of writing/reading data to and from the memories MAL to MB2 in the sector shuffle circuit 14 in the so-called D2 format described above is very tight, and sometimes in the case of the PAL system described above, As is clear from FIG. 8, there is little time margin. Moreover, since the actual writing timing of video data shifts several degrees depending on the color field sequence, there is even less margin. Moreover, if there is a phase shift between the input video signal and the recording reference signal, a situation may occur in which the write operation and the read operation overlap, and there is a risk that normal operations will not be performed.

In addition, a delay circuit 17 is required to correct the recording phase difference caused by the difference in the position of the recording heads of channels O, L, and α and the shift in the start timing of hend sliding contact, and a delay memory is required for this purpose. Become.

The present invention has been made to solve these drawbacks, and it not only makes it possible to expand the time margin for corrupting/reading data from the memory, but also corrects the recording phase difference between recording channels. The purpose of the present invention is to provide a data encoding circuit that can be used for both functions and eliminates the need for a delay memory dedicated to the correction.

(Means for Solving the Problems) As shown in FIG. 1, the data encoding circuit according to the present invention converts input digital signals for l fields into at least two
distribution to two recording channels (for example, channels 0 and 1) and a predetermined number (for example, 4 in the case of PAL system, 4 in the case of NTS,
In the case of the C method, in the data encoding circuit that divides the recording signal into recording blocks (video sectors) and shuffles (sector shuffling) to block encode the divided signal (3), at least three memories for shuffling are provided. In addition to the block configuration (sector memories MA 1 -MA 3 or MB 1 -?IB3), the memory of at least one recording channel (MB l -MB3)
) from the other memory (MA 1
The above-mentioned problem is solved by correcting the recording phase difference between the recording channels with a delay compared to the timing of reading from -MA 3 ).

[Operation] Shuffling memory is 3 blocks (3 video sectors)
By adopting this configuration, the time margin for writing to and reading from the memory is expanded, the allowable phase shift amount between the manual digital signal and the recording reference signal is expanded, and the position between the recording heads for each recording channel is increased. By correcting the recording phase difference based on the difference in the recording phase difference using the same memory, there is no need to provide a separate delay memory for correcting the recording phase difference.

〔Example〕

FIG. 1 is a Bronnok circuit diagram showing a data encoding circuit as an embodiment of the present invention. The data encoding circuit of this embodiment is a so-called D2 Forman digital VT.
It is preferable to apply it to a recording-side encoder circuit of a video tape recorder.

In FIG. 1, a digital video signal whose I sample node is 8 bits (l height) is supplied to the input terminal II. This input video signal '7' V in
is sent to the line shuffling circuit l2, and the valid data in the l line is shuffled.

The outer ECC encoder 13 sends the shuffled valid data to two channels, namely channel 0.
and channel 1, the data of each channel is divided into six equal parts, a 4-byte outer parity code is added, and the data is sent to the sector shuffle circuit 10 for each channel. The above is the same as the explanation of FIG. 4 described above.

The memory in the sector shuffle circuit 10 is composed of three blocks for each channel, each having a memory capacity of three sectors. In other words, three sector memories MAI to M^3 are provided for channel 0, and three sector memories MBI to MB3 are provided for channel 1, and for these memories MAI to MB3, Well, second
Write (W) and read (R) at the timing shown in the figure.
) is controlled. For example, for sector memory old 1 to gate ^3 of channel O, while writing to memory MA + and gate A2, reading from memory MA3,
While writing to memories MA2 and MA3, memory MA
It is controlled to read from memory MA2 while writing to memory gate A3 and gate AI.

The same company is also responsible for the sector memories MB1-MB3 of JanFu1. This allows each memory to be occupied (
The time margin for W)/readout (R) is greatly increased, and it goes without saying that it is necessary to deal with the shift of several lines in the aging timing due to the color field no-ken mentioned above.
Even if a phase shift occurs between the input video signal and the recording reference signal supplied to the terminal 32, it is possible to sufficiently cope with the phase difference, for example, up to a phase difference of about ten or more lines, and the amount of permissible phase shift can be expanded. Further, a timing generation circuit 33A for channel 0 and a timing generation circuit 33B for channel l are provided independently, and the sector memories M81 to MB of channel l are provided independently.
By delaying the read timing for channel O from the memory read timing for channel O by the rotational phase difference between the head pair 1{A, HB (or between HC and tLD), a delay device 36 using, for example, a counter is provided. The above-mentioned head rotation phase difference can be compensated for by this simple arrangement, and the delay circuit 17 shown in FIG. 4 is no longer necessary, making it possible to greatly simplify the circuit configuration. Note that the other configurations and operations in FIG. 1 are similar to those of the circuit in FIG. 4 described above, so corresponding parts are given the same reference numerals and explanations will be omitted. Here, sector memory MAL to gate A3 (or MB1
-MB3), the available memory I
Since the capacity of c is usually a power of 2, conventional two sector memories MAI-MA2 (or MBI-
MB2), three sector memories MAI-MA3 (or MBI to MB3) are used as in this embodiment.
It can be seen that there is no increase or decrease in the number of parts (number of memory ICs) even when using . That is, the capacity of sample data for one video sector is 37,848 bytes in the PAL system (34,680 bytes in the NTSC system, hereinafter the same), and is 75,696 (69,360) bytes in the case of two sectors. This is larger than 2''' = 65536, so as a memory IC, 2 '' = 131072
I have no choice but to use a part-time job. On the other hand, as in this embodiment, 3 video sectors have 113,544 (10
4040) To obtain the memory capacity of the height, perform the above 2.
''' = 131072 bytes of memory IC is sufficient, so there is no need to increase the number of memory devices when constructing an actual circuit.The divided form or manoping form of the memory device in this case is shown in Figure 3. show.

In FIG. 3, each memory block Ml-M3 is connected to each sector memory MAI-M^3 (or MBI-M3).
B3), and the figure shows the numerical values for the PAL system, and the numerical values for the NTSC system are shown in parentheses. It should be noted that the present invention is not limited to the above-described embodiment, and for example, the audio shuffling memory may be provided separately (commonly) within the same memory IC. The memory may be configured with four blocks (four sectors) or more. It goes without saying that various other changes can be made without departing from the spirit of the invention.

[Effects of the Invention] According to the data conversion circuit of the present invention, three broncs (3
By adopting a video sector (video sector) configuration, the time margin for writing/reading data to and from memory is greatly increased, and, for example, the tolerance for the phase shift between the human-powered digital signal and the recorded reference signal can be greatly expanded. In addition, since the above memory can be used to simultaneously correct recording timing deviations caused by differences in the position of the recording head for each recording channel, it is necessary to provide a separate delay memory to correct the deviations. The circuit configuration can be simplified.

[Brief explanation of the drawing]

Fig. 1 is a bronch circuit diagram showing a schematic configuration of an embodiment of a data encoding circuit according to the present invention, Fig. 2 is a time chart for explaining the operation, and Fig. 3 is a division of memory devices constituting a sector memory. FIG. 4 is a bronch circuit diagram showing a conventional example of a data encoding circuit as an encoder circuit provided on the recording side of a digital VTR, and FIG. Fig. 6 is a diagram showing the channel distribution and segment division of valid data within one field; Fig. 7 is a diagram showing the arrangement state of sample data within one sector and synchronization blocks; Fig. 8 is a diagram showing the parity block. is a time chart for explaining the write/vt output operation and recorded data for each sector memory in the sector shuffle circuit,
FIG. 9 is a time chart showing recording data corresponding to recording tracks, FIG. 10 is a schematic plan view of the rotary head device,
FIG. 11 is a schematic front view showing a recording track pattern on a magnetic tape. IO......Sector shuffle circuit 11...
...Video input terminal l2...Line shuffle circuit l3...
...Outer ECC addition circuit 14...Sector shuffle circuit 1 6 A, 1 6 B...
...SYNC. IO, {Inner ECC addition circuit 17...
...Delay circuit 2l ...Audio human power terminal 24 ...
...Outer ECC addition circuit 25 ...Audio shuffle circuit MAI to MB3 ... Sector memory 3l, 33 ... Timing generation circuit -49
7-

Claims (1)

[Claims:] A data encoding circuit that distributes one field worth of input digital signal to at least two recording channels, divides it into a predetermined number of recording blocks, and shuffles the divided signal for block encoding. Data encoding characterized in that the memory for shuffling has a configuration of at least three blocks, and the timing of reading from the memory of at least one recording channel is delayed to correct the recording phase difference between the recording channels. circuit.