JPH03192597A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To contrive high-speed transition time of a word driver from ON to OFF state i.e. the access time by providing a resistor between an emitter and a grounded end of a transistor for sense current attraction at a word driver circuit. CONSTITUTION:A final stage transistor Q3 of the word driver including plural Darlington connection NPN transistors is connected to its collector to a row line, its emitter to the grounded end through the resistor RE. By making the RE value to the proper value when the transistor Q3 becomes ON state, the collector potential can be shifted by potential drop generating at the resistance RE to high direction, the rise of row line X become fast, the passing time of the sense current to a memory side is shortened, therefore the rise of the voltage of a connecting point 1 become fast, and the acceleration of the transition time of output terminal of from H level to L level is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory circuit, and particularly to an electrically writable programmable read-only memory (hereinafter referred to as FRO).
The present invention relates to a word driver circuit (referred to as M).

[Conventional technology]

FROM, especially junction-destructive bipolar FROM made in a bipolar integrated circuit manufacturing process, is widely used in a wide range of information processing devices, control devices, etc. because of its flexibility in allowing users to freely write its memory contents. There is. The entire circuit of such FROM is shown in FIG. That is, during writing, write terminal lO - write circuit 6 - memory cell matrix 7 - word driver circuit 5
Writing is performed by flowing a write current of about 100 to 200 mA through the path. The memory cell is a base open transistor Q as shown in FIG. 4(a).

The emitter of the transistor is connected to the column line Y, and the collector thereof is connected to the row line X. By flowing a write current from the write circuit through the column line Y, the emitter-base junction of the base open transistor is short-circuited to perform writing. The equivalent circuit of the memory cell after writing is shown in FIG. 4(b).

A word driver circuit for driving the row line is provided at one end of the row line The sense current is absorbed in the path from 8 to the written memory cell to the row line

Generally, due to area constraints, a typical FROM word driver circuit has a circuit configuration as shown in FIG. 2, which is relatively simple and has a small number of elements.

The word driver circuit in Figure 2 is an NPN transistor Ql.
, Qz, and Qs are Darlington-connected and each collector is connected to the power supply voltage via a resistor.The output of the word driver circuit is as follows: the collector of the NPN transistor Q3 is connected to the row line Diode D1
It is pulled up via resistor R4. In Figure 2 D D
1 to DDゎ are diodes forming a decoder circuit for selecting one word driver circuit from among a plurality of word driver circuits, QDr is a written memory cell, and a sense circuit is formed by diode D2 and resistor R7. is formed. Resistors Rs and Re of the word driver circuit are transistors Q! , Q3 for limiting the base current, and the diode D1 are Schottky barrier diodes for preventing backflow.

If the memory cell connected to the selected word driver circuit has been programmed, the resistor R in FIG. ), the sense current flows through the path, but does not flow to the output circuit side. In this case, the "H" level is normally output to the output terminal. On the other hand, when the memory cell is unwritten, no current path occurs between the column line Y and the row line X, so the current through the resistor R7 does not flow toward the diode D2 but toward the output circuit.

In this case, the "L" level is normally output to the output terminal, which is the opposite of the above. Here, the output terminal changes from “H” level to “L” level.
"Considering the case where the transition is made to the "H" level, the previously written cells will become unselected, and the unwritten cells will be newly selected. In this case, the "H" level of the output terminal
In order to speed up the transition time from "level" to "L" level, the potential at connection point 1 in Figure 2 should be inverted from "H" level to "L" level by the output circuit connected beyond it. However, if the word driver circuit is turned off, that is, if the transition time from the "L" level to the "H" level of the output of the word driver circuit is slow, the potential of the row line Since the rising edge of is delayed, a part of the sense current continues to flow from the memory cell QD1 to the word driver circuit side, and a sufficient sense current does not flow to the output circuit side.As a result, the connection point 1 in FIG. In other words, the transition time from the "H" level to the "L" level of the output terminal is longer than the "L" level of the output of the word driver circuit that absorbs the sense current through the written memory cell. ” to the “H” level transition time.

As mentioned above, the FROM word driver circuit is shared for both writing and reading, so it is necessary to absorb a large current during writing, so the NPN shown in Figure 2 is used.
As the transistor Q, a transistor having a relatively large area is often used, and parasitic capacitance such as the junction capacitance of the transistor tends to increase. Furthermore, as the memory capacity increases, the capacitance attached to the row line X also tends to increase, so the output of the word driver circuit as shown in FIG.
The transition time from L" level to "H" level is determined by the time constant of resistor R4, transistor Q3, and parasitic capacitance attached to row line X in FIG. 2, but as these capacitances increase, charging time increases. As the transition time becomes longer, the transition time increases.

As a method of shortening this transition time, it is possible to reduce the value of the resistor R4 in FIG. 2 as much as possible, but there is a limit in terms of power consumption of the circuit. or,
Another method is to make the output of the word driver a totem pole type and use the driving force of an NPN transistor provided between the power supply and the row line X.
This is not necessarily a good method because the area of the word driver circuit increases as the number of elements increases.

As mentioned above, in the conventional FROM word driver circuit, the transition time from the "L" level to the "H" level of the word driver output increases, so that the output terminal changes from the "H" level to the "L" level. This method has the disadvantage that the transition time is delayed and the access time increases.

[Problem to be solved by the invention]

In the conventional FROM as described above, the transition time from the "L" level to the H level of the output of the word driver circuit used therein is determined by the resistance R4 connected to the row line X via the diode D1 and the transistor Q3. Since it is determined by the time constant of the capacitance attached to the row line X and the capacitance attached to the row line The disadvantage is that it is slow.

[Means to solve the problem]

The semiconductor memory circuit of the present invention includes a word driver circuit including a plurality of Darlington-connected NPN transistors, the collector of the final stage transistor of the NPN transistor is connected to a row line, and the emitter is connected to a ground terminal via a resistor. have

〔Example〕

Next, a FROM word driver circuit according to the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a FROM word driver circuit according to an embodiment of the present invention. In this embodiment, the emitter of a transistor Q whose collector is connected to the row line X and whose base is connected to the emitter of the preceding transistor is connected to GND via a resistor R8. Elements other than this resistor RR are completely the same as the conventional example shown in FIG.

Now, consider a case where a written memory cell is selected. That is, a sense current flows from the power supply voltage through the resistor R2 of the sense circuit through the path from the diode D2 to the memory cell QD1 to the corephthal transistor Q of the transistor Q and the emitter resistor R8 to GND. If the power supply voltage is calculated assuming that the forward ON voltage of the diode containing the 5V1 memory cell is 0.8V, and the voltage between the collector and emitter of the transistor in the ON state is 0.2V, then the sense current is calculated as shown in the conventional diagram of Fig. 2. In the FROM word driver circuit, Is'' (Vcc O, 8X2 0.2)/Ry, and if R, = 20 kΩ, I, = 160 μA. This means that the output is 1 bit, that is, 1 memory cell. In this case, if the output is 8 bits and the memory cell is 8 bits co-written, the sum of the sense currents is 16
0μAX8=1.28mA, and this current is the row line
It flows to the emitter (GND) of the corephthal transistor Q3 of the transistor Q3. At this time, the output of the word driver circuit, that is, the potential of the collector of the turned-on transistor Q is approximately 0.2V.

Here, when this word driver circuit, which had been in a selected state until then, becomes a non-selected state, the potential of the collector of the transistor Q mentioned above changes from the "L" level to the "H" level, for example, as shown in FIG. Transition to. The time constant of this rise is determined by the value of the resistor R4 in FIG. 2, the row line X to be charged, the capacitance attached to the memory cell, etc.

Next, in the FROM word driver circuit according to the present invention, in the selected state, the corephthal resistor R3 of the transistor Q3 is
The current flowing through ~GND causes a potential drop across the resistor R8. That is, the potential of the collector of the transistor Q in the FROM word driver circuit according to the present invention can be expressed as 0.2 V + I s X Rz, and R,! By setting the value of to an appropriate value, it becomes possible to shift the potential of the collector of the transistor Q, Q when it is on, to a higher side by the amount of the potential drop that occurs in the resistor R8. This shift amount is I s X in the above formula
Corresponds to Rz.

Resistance R1! The output of the word driver circuit depending on the presence or absence of = from the “L” level of the collector potential of transistor Q3 to “
FIG. 5 shows the transition to H'' level. In FIG. 5, ΔV = I s X Rz.

Assuming that the other resistances and capacitances are the same and the time constant remains unchanged, the output of the word driver circuit = transistor Q
The time it takes for the collector potential of No. 3 to reach a certain potential (VO in Figure 5) is shorter by Δt when the "L" level potential is higher by the potential drop that occurs in resistor R8. . In other words, since the rise of the row line X becomes faster, the time during which the sense current flows to the memory cell side becomes shorter, and the rise of the voltage at the connection point 1 in FIG. 1 becomes faster. That is, the voltage at the connection point l in FIG. 1 is the voltage at which the output terminal is inverted from the "H" level to the "L" level (
For example, the time required to reach vo) in FIG. 5 becomes shorter, and the transition time from the "H" level to the "L" level at the output terminal becomes faster.

A current of 5 to 10 mA usually flows through the resistor R8, which is the sum of about 1 mA of the sense current flowing from the memory cells and a leakage current flowing from the word driver circuit in the non-selected state. The value of the resistor R8 for shifting the "L" level of the reflector-row line X of the transistor Q in FIG. 2 to a higher level by, for example, 0.1 V may be 10 to 20 Ω.

Of course, it is needless to say that the resistor R8 does not need to be provided for every word driver, and may be provided on one side in common.

〔Effect of the invention〕

As explained above, the present invention can switch the word driver from ON to OFF by simply providing a resistance of about 10 to 20Ω between the emitter of the transistor for absorbing the sense current and GND in the conventional word driver circuit.
In other words, since the transition time from the "L" level to the "H" level of the row line is fast, the output terminal's "H" level to "L" level when the memory cell is selected from already written to red writing. This has the effect of speeding up the transition time to a level.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a word driver circuit of a FROM according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a word driver circuit of a conventional FROM, and FIG. 3 is a diagram showing the entire circuit configuration of a FROM. Figure 4 is a circuit diagram of a FROM memory cell.
FIG. 5 is a diagram showing the temporal change in the potential of the row line during the transition from ON to OFF of the word driver circuit. 1... Connection point between the sense circuit and the output circuit, 2.
...Input terminal, 3...Input circuit, 4...
...Chip select circuit, 5...Word driver circuit, 6...Write circuit, 7...
・Memory cell matrix, 8... sense circuit,
9...Output circuit, 10...Output terminal,
DI-D2- DDI~DD,...Diode %QO...Unwritten memory cell, Qlt Qs
, Qs...NPN transistor, QD, QD
, ...written memory cells, R1 to Rt,
RK...Resistance.

Claims (1)

[Claims] A semiconductor memory comprising a word driver circuit including a plurality of Darlington-connected NPN transistors, a collector of a final stage transistor of the NPN transistors being connected to a row line, and an emitter connected to a ground terminal via a resistor. circuit.