JPH0319424A - Output buffer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an output bass sofa that reduces noise generated in a power supply line when the output of an LSI changes.

2. Description of the Related Art In recent years, as LSIs have become more highly integrated, the number of output terminals built into them has also tended to increase. However, it has become impossible to ignore the malfunction of LSIs due to noise generated by simultaneous changes in the outputs of many terminals, especially noise generated in the power supply line.

The output stage used in a conventional LSI and the noise generated thereby will be explained below.

FIG. 3 is an example of a conventionally commonly used output circuit. IN is an input terminal, OUT is an output terminal, I
N 'l/2', I N v3', r N v,
a' each indicates an inverter. INV
4' has higher driving ability than INV2' and INV3'. This is because INV4' drives an external load, and the reason why the driving ability of INV2' and INV3' is low is to reduce the fan-in of this circuit.

FIG. 4 shows the I N v4' part in this circuit diagram in detail.

Press the button N3 in Figure 4, and the OUT is N3, OUT in Figure 3.
is equivalent to TP1 is a P channel transistor, T
N1 is an N-channel transistor. vDD1, vS
S1 is the power supply line inside L13I CH7', P13S is the power supply pin of the LSI package, and POUT is the output pin of the LSI bus cage. Between OUT and load OL, it is considered that the bonding wire and the resistance ROUT of the lead frame and the inductance Lotr'r are connected in series. Also, the power supply lines VDD1 and VSS1 inside the LSI chip
There are also parasitic resistances RVDD, RVf3S and inductances L'iDD between and the external power supply lines VDD and VSS,
L”lf3S is added.

Here, when N3 changes from the "H" state to the "L" state, the output is l? Changes from L% state to "H" state. At this time, the current flowing from VDD to OL through TP1 is Ip
, If the voltage change is Jlh, ,{%'lh=RVDD
-1p-1-LvDD-, {Ip/7t...
...(1) Noise as expressed by the following is generated. JIp/It represents the average rate of change in current Ip over Jt time. Output is ゛H
Similarly, when changing from “L” state to “L” state, JVhl=RV$8-In-1-LVSS-J n/A
FIG. 5 shows the voltage waveforms of POUT, PVDD, and P/8S (7) as a result of the change in ON3 that causes noise as expressed by t... (2). If there are n output stages that change, the noise will be multiplied by n. This is because Ip and In are multiplied by n. 1
In addition, these noises become larger as the driving capability of the output stage becomes larger.

Noise on the power supply line reduces the input voltage margin and
This may cause the I to malfunction. Further, noise on the output line causes malfunction of the next stage LSI.

Conventionally, these noises have been prevented by increasing the number of power supply terminals.

Problems to be Solved by the Invention However, in the conventional structure described above, as the number of output terminals that change simultaneously increases, the number of power supply terminals also increases, and the number of terminals and chip size increase, leading to an increase in cost. Another problem is that the terminals of the package cannot be used effectively.

The present invention solves the above-mentioned conventional problems, and aims to reduce noise and prevent malfunctions without increasing the number of power supply terminals.

Means for Solving the Problems In order to achieve this object, the output circuit of the present invention connects a plurality of inverters in parallel, the first inverter always switches a certain period of time earlier than the remaining inverters, and the first
After one inverter switches and until the remaining inverters switch, the remaining inverters temporarily enter a high impedance state.

Function: With this structure, the noises generated by the plurality of inverters cancel each other out, and the noise generated in the power supply can be reduced. Furthermore, in the period 1 in which the remaining inverters switch after the first inverter switches, the remaining nine inverters are in a high impedance state, so that no increase in current consumption occurs.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of an output circuit in a first embodiment of the present invention.

In FIG. 1, IN represents an input terminal, OUT represents an output i, INV1, xNV2, XNV3, and INV4 each represent an inverter, and Xx1 represents an exclusive OR gate. It also has a INV4} license state input. IN'1
1, IN” i4 has a high driving capacity, but the IN” in Fig. 3
It is about half of V4'.

FIG. 2 shows the operation of FIG. IN is *H n
When the state changes from the state to the NLPI state, switching of rNV1 begins. At this time, INV3f'l-i2 has not changed, so the output power of ICX1 is in wHs state, and INV4 is in a high impedance state. Thus O
The potential of the UT begins to rise and noise occurs on the power supply line. However, the noise generated by INV1 is I N in Figure 3.
This is about half of the noise generated by V4'. This is because the driving capacity is small.

On the other hand, when INV3 switches, ICX1 switches again.
Ox becomes L” state and INV4 starts switching.
The switching timing of sv4 is set to be delayed by half a cycle of the noise generated by XNV1. By doing so, the noise generated by INV1 and INV4 (LvDD-dp/Jt in equation (1)) works to cancel each other out, and the overall noise can be reduced compared to the conventional circuit.

The switching timing of INV1 and INV4 is IN
Y2, INV3, RX1 (adjusted with D delay'lk. Also, the driving capabilities of INV1 and INY+ do not have to be the same, and may be adjusted to further reduce noise.

Noise is similarly reduced when IN changes from the "L" state to the "H" state.

FIG. 6 shows a circuit diagram of an output circuit in a second embodiment of the invention.

For Figure 6, IN is an input terminal, OUT is an output terminal,
I N V 1 to I N V 9 are { 7 hearts, K
X1, ]KX2 are exclusive OR gates. Engineering Nv1,
The switching timing of INV4 and INVs is
It is desirable that the period be about one-third of the period of the generated noise.

There may be more tri-state inverters with different timings.

Effects of the Invention By doing so, the noise generated in the power supply line can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the output circuit in the first embodiment of the present invention, FIG. 2 is a voltage waveform diagram at each part of FIG. 1, and FIG.
The figure is a circuit diagram of a conventional output circuit, and Figure 4 is the I of Figure 3.
6 is a detailed circuit diagram of the portion N V 4', FIG. 6 is a voltage waveform diagram of each portion in FIG. 4, and FIG. 6 is a circuit diagram of the output circuit of the second embodiment of the present invention. IN...Input terminal, OUT...Output terminal, INY1, INV2, INY3, INV4
．． ．． ．． ．． ．． ．． Inverter, Ex1...Exclusive O
R gate.

Claims (1)

[Claims] It has a plurality of inverters connected in parallel, and the first inverter always switches at a faster timing than the remaining inverters, and from the time the first inverter switches until the remaining inverters switch, the remaining inverters An output buffer that temporarily enters a high-impedance state.